Vertical type semiconductor device provided with an improved
construction to greatly decrease device on-resistance without impairing
breakdown
    81.
    发明授权
    Vertical type semiconductor device provided with an improved construction to greatly decrease device on-resistance without impairing breakdown 失效
    垂直型半导体器件具有改进的结构,以大大降低器件导通电阻而不损害击穿

    公开(公告)号:US5504360A

    公开(公告)日:1996-04-02

    申请号:US293421

    申请日:1994-08-22

    摘要: A vertical type semiconductor device is provided with an improved construction which greatly decreases the on-resistance without impairing the breakdown voltage thereof. In the fundamental DMOS cells that control a current to constitute the vertical semiconductor device, through-hole cells are arranged along the sides of a cell having a channel. The through-hole cell includes a through-hole extending from the surface of an n.sup.- -type drift region toward an n.sup.+ -type drain region, and also includes an n.sup.+ -type through-hole region that is formed by diffusing impurities from the inner wall of the through-hole which is continuous with the n.sup.+ -type drain region. A breakdown voltage of the element is maintained by the n.sup.- -type drift region between a p-type well region and the n.sup.+ -type through-hole region or the n.sup.+ -type drain region. Given the unique arrangement of the through-hole cells, the JFET resistance component becomes negligibly small between the DMOS cells neighboring along the sides of the cells despite the fact that the cells are finely formed, and a small on-resistance is exhibited.

    摘要翻译: 垂直型半导体器件具有改进的结构,其大大降低导通电阻而不损害其击穿电压。 在控制电流以构成垂直半导体器件的基本DMOS单元中,沿着具有沟道的单元的侧面布置有通孔单元。 通孔单元包括从n型漂移区域的表面向n +型漏极区域延伸的通孔,还包括通过从内部扩散杂质形成的n +型通孔区域 与n +型漏极区连续的通孔的壁。 元件的击穿电压由p型阱区域和n +型通孔区域或n +型漏极区域之间的n型漂移区域维持。 鉴于通孔单元的独特布置,尽管细胞形成细小,但是出现小的导通电阻,但是JFET电阻分量在沿着单元侧面相邻的DMOS单元之间变得可以忽略不计。