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公开(公告)号：US20220352855A1
公开(公告)日：2022-11-03
申请号：US17243762
申请日：2021-04-29
Applicant: Micron Technology, Inc
Inventor： Wei Lu Chu , Dong Pan
Abstract: Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.
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公开(公告)号：US20220343964A1
公开(公告)日：2022-10-27
申请号：US17864237
申请日：2022-07-13
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C11/4074 , G11C11/4091 , H03H7/06 , G11C5/14 , G11C7/14 , G05F1/575 , G11C11/4063
Abstract: Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.
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公开(公告)号：US20220157368A1
公开(公告)日：2022-05-19
申请号：US16950593
申请日：2020-11-17
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C11/4091
Abstract: Methods, systems, and devices for voltage drop mitigation techniques for memory devices are described. A memory device may include an array of memory cells, a conductive line, a pull-up circuit, and an output circuit. The conductive line may be configured to convey a first voltage for performing an operation with the array of memory cells. The pull-up circuit may be configured to couple the conductive line with a voltage source during at least a portion of a duration in which the operation is performed based on a first signal that enables applying a current to the array of memory cells as part of the operation. The output circuit may be configured to output a second signal to deactivate the pull-up circuit before the operation is complete. Outputting the second signal may be based on the first signal and a difference between the first voltage and a reference voltage.
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公开(公告)号：US20220157365A1
公开(公告)日：2022-05-19
申请号：US16952804
申请日：2020-11-19
Applicant: Micron Technology, Inc.
Inventor： Zhi Qi Huang , Wei Lu Chu , Dong Pan
IPC: G11C11/4076 , G11C11/22
Abstract: Methods, systems, and devices for timing signal delay for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. A memory device may include delay components having a configurable impedance based at least in part on one or more fabrication characteristics of the memory device, one or more operating conditions of the memory device, one or more bias voltages, or a combination thereof.
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公开(公告)号：US20220076720A1
公开(公告)日：2022-03-10
申请号：US17526846
申请日：2021-11-15
Applicant: Micron Technology, Inc.
Inventor： Zhi Qi Huang , Wei Lu Chu , Dong Pan
Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.
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Patent Agency Ranking
公开(公告)号：US20220068345A1
公开(公告)日：2022-03-03
申请号：US17003163
申请日：2020-08-26
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C11/4074 , H03H7/06 , G11C11/4091
Abstract: Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.
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公开(公告)号：US11257558B1
公开(公告)日：2022-02-22
申请号：US16988285
申请日：2020-08-07
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
Abstract: Methods, systems, and devices for protecting components in memory from overvoltage are described. A memory system may include a voltage regulator coupled with a first voltage source and a reference circuit that is configured to output a reference signal for the voltage regulator. The reference circuit may include a transistor that is used to generate the reference signal. The memory system may also include a protection circuit that is configured to maintain a voltage between a gate of the transistor and a second node of the transistor below an upper voltage limit. The protection circuit may include a comparator that is configured to compare a difference between a voltage of the reference signal output by the reference circuit and a voltage of the first voltage source with a reference voltage. The comparator may control a pull-down circuit coupled with the output of the reference circuit based on the comparison.
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公开(公告)号：US11119523B2
公开(公告)日：2021-09-14
申请号：US16146982
申请日：2018-09-28
Applicant: MICRON TECHNOLOGY, INC.
Abstract: A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.
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89.发明授权公开(公告)号：US10658929B2
公开(公告)日：2020-05-19
申请号：US16283230
申请日：2019-02-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yuanzhong Wan , Dong Pan
Abstract: According to one embodiment of this disclosure, an apparatus is disclosed. The apparatus includes a voltage regulator configured to produce a regulated voltage, a plurality of current circuits coupled in parallel between an output node and a power node, each of the plurality of current circuits including first and second transistors coupled in series, the first transistor of each of the plurality of current circuits being biased with the regulated voltage, and a control circuit configured to activate the second transistor of selected one or ones of the plurality of current circuits responsive, at least in part, to a voltage at the output node.
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公开(公告)号：US10651732B2
公开(公告)日：2020-05-12
申请号：US16413721
申请日：2019-05-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Ming H. Li , Dong Pan
Abstract: Methods of operating a charge pump, and charge pumps configured to perform similar methods, involve monitoring a level of a supply voltage of the charge pump, and turning off an oscillator of the charge pump responsive to the level of the supply voltage dropping below a certain level, wherein turning off the oscillator comprises setting an inverter in a ring oscillator loop of the oscillator to a steady state output.
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