摘要:
A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.
摘要:
A method for improving performance in exponentiation algorithms for encryption programs such as the Diffie-Hellman key-exchange protocol. The program determines if a standard exponentiation algorithm or an algorithm optimized for reduced memory are optimal for a given circumstance. The optimized algorithms may use zero-biased exponents to minimize the number of precomputed vectors needed and the number of multiplication operations required.
摘要:
A method and apparatus to compute a Q syndrome for RAID 6 through the use of AES operations is provided. In an embodiment, the result of GF multiplication performed using the AES operations allows RAID-6 support to be provided without the need for a dedicated RAID controller.
摘要:
A cryptographic system for encrypting a data stream to be transported over a network by using a one way hash function constructed according to Merkle-Damgard construction includes a plurality of Davies-Mayer structure modules. A Davies-Mayer module modifies two variables A and B according to at least four words by no more than three Advanced Encryption Standard (AES) block cipher rounds.
摘要:
In some embodiments, an apparatus and method for speeding up the computations for characteristic 2 elliptic curve cryptographic systems are described. In one embodiment, a multiplication routine may be pre-computed using a one iteration graph-based multiplication according to an input operand length. Once pre-computed, the multiplication routine may be followed to compute the products of the coefficients of the polynomials representing a carry-less product of two input operands using a carry-less multiplication instruction. In one embodiment, the pre-computed multiplication routines may be used to extend a carry-less multiplication instruction available from an architecture according to an input operand length of the two input operands. Once computed, the carry-less product polynomial produces a remainder when the product is computed modulo a programmable polynomial that defines the elliptic cryptographic system to form a cryptographic key. Other embodiments are described and claimed.
摘要:
In one embodiment, an encryption operation may be performed by obtaining a product of a carry-less multiplication using multiple single instruction multiple data (SIMD) multiplication instructions each to execute on part of first and second operands responsive to an immediate datum associated with the corresponding instruction, and reducing the product modulo g to form a message authentication code of a block cipher mode. Other embodiments are described and claimed.
摘要:
A method, apparatus and system for multiplying a matrix by a vector, for example, video interpolation (other applications are contemplated). The matrix may be a representation of a large and sparse system of linear equations. The large and sparse system of linear equations may be used to estimate motion between frames of a video file for converting frame rates. The vector may be a first estimation of a solution to the system of linear equations. The matrix may be multiplied by elements of the vector in an order different from the order in which the elements are arranged in the vector. Elements in the vector may be multiplied in parallel. A second vector estimation of the solution to a system of linear equations may be a product of the multiplying. The solution to the system of linear equations may be set, for example, when the first and second vector estimations differ by less than a predetermined amount. Other embodiments are described and claimed.
摘要:
A method for protecting private data from cache attacks is disclosed. One embodiment includes storing private data in a protected cache line to protect it from cache attacks, receiving a snoop request to the protected cache line, and responding to the snoop request with a miss.
摘要:
An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
摘要:
Instructions and logic provide general purpose GF(28) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix is applied to each element of the source data operand, and the translation vector is applied to each of the transformed elements. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD binary finite field multiplicative inverse to compute an inverse in a binary finite field modulo an irreducible polynomial for each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.