公开(公告)号：US5247627A

公开(公告)日：1993-09-21

申请号：US750478

申请日：1991-08-27

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

公开(公告)号：US4933761A

公开(公告)日：1990-06-12

申请号：US187052

申请日：1988-04-27

申请人： Tokumichi Murakami ,  Kohtaro Asai ,  Atsushi Itoh ,  Masami Nishida ,  Naoto Kinjo ,  Kenichi Asano

发明人： Tokumichi Murakami ,  Kohtaro Asai ,  Atsushi Itoh ,  Masami Nishida ,  Naoto Kinjo ,  Kenichi Asano

IPC分类号： G06T9/00 ,  H03M7/30 ,  H04N7/24 ,  H04N7/26 ,  H04N7/28 ,  H04N7/36 ,  H04N7/46 ,  H04N7/50

CPC分类号： G06T9/008 ,  H03M7/3082 ,  H04N19/124 ,  H04N19/132 ,  H04N19/137 ,  H04N19/147 ,  H04N19/149 ,  H04N19/176 ,  H04N19/51 ,  H04N19/587 ,  H04N19/61 ,  H04N19/80 ,  H04N19/94 ,  H04N21/23406 ,  H04N21/44004 ,  H04N19/146 ,  H04N19/152

摘要： In an image coding and decoding device, input digital image signals are divided into blocks of prescribed size, and coding processing is performed on differential signals taken between the input block signal and interframe forcasting signals thereby enabling efficient transmission to be performed.