公开(公告)号：US5206940A

公开(公告)日：1993-04-27

申请号：US750512

申请日：1991-08-27

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

公开(公告)号：US5247627A

公开(公告)日：1993-09-21

申请号：US750478

申请日：1991-08-27

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

公开(公告)号：US5237667A

公开(公告)日：1993-08-17

申请号：US755503

申请日：1991-08-27

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

公开(公告)号：US5045993A

公开(公告)日：1991-09-03

申请号：US201208

申请日：1988-06-03

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/345 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

公开(公告)号：US5222241A

公开(公告)日：1993-06-22

申请号：US750408

申请日：1991-08-27

申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

公开(公告)号：US4686286A

公开(公告)日：1987-08-11

申请号：US735561

申请日：1985-05-17

申请人： Toshio Niwa ,  Yoshiaki Katoh

发明人： Toshio Niwa ,  Yoshiaki Katoh

IPC分类号： C09B62/44 ,  C09B62/513 ,  D06P1/384 ,  D06P3/66

CPC分类号： C09B62/4415 ,  C09B62/513

摘要： A disazo reaction dyestuff for cellulose fibers which is of the formula: ##STR1## wherein D is a residue of a monoazo dye, R.sup.1 is hydrogen or lower alkyl, and X is a group: ##STR2## wherein R.sup.2 and R.sup.3 are each hydrogen, methyl, methoxy or --SO.sub.3 M, Y is an aromatic or aliphatic divalent residue and M is hydrogen or an alkali metal.

摘要翻译： 用于纤维素纤维的双重反应染料，其具有下式：其中D是单偶氮染料的残基，R1是氢或低级烷基，X是一个基团：其中R2和 R 3各自为氢，甲基，甲氧基或-SO 3 M，Y为芳族或脂族二价残基，M为氢或碱金属。

公开(公告)号：US4256963A

公开(公告)日：1981-03-17

申请号：US80025

申请日：1979-09-28

申请人： Sadao Takahashi ,  Yoshiaki Katoh

发明人： Sadao Takahashi ,  Yoshiaki Katoh

IPC分类号： H01J49/32 ,  G01N27/62 ,  H01J49/02 ,  B01D59/44

CPC分类号： H01J49/022

摘要： A linked scan type mass spectrometer wherein the mass number of a metastable ion originating from a precursor ion is measured by scanning the magnetic and electric fields at a constant ratio between the two fields. Calculation is performed on a first electrical signal representative of the mass number of the precursor ion, a second electrical signal corresponding to a value of the electric field at which the mass number of the precursor ion is detected, and a third electrical signal corresponding to a value of the electric field at which the metastable ion is detected during scanning of the electric field and magnetic field, to thereby determine the mass number of the metastable ion. The third electrical signal is obtained by measuring a value of the magnetic field which contributes to the dispersion of ions. Means is provided for correcting the measured value of the magnetic field, thereby determining the mass number of the metastable ion with high accuracy.

摘要翻译： 一种链式扫描型质谱仪，其中通过以两个场之间的恒定比例扫描磁场和电场来测量源自前体离子的亚稳离子的质量数。 对表示前体离子的质量数的第一电信号进行计算，对应于检测到前体离子的质量数的电场的值的第二电信号和对应于前体离子的第三电信号 在扫描电场和磁场期间检测亚稳离子的电场的值，从而确定亚稳离子的质量数。 通过测量有助于离子分散的磁场的值来获得第三电信号。 提供用于校正磁场的测量值的装置，从而以高精度确定亚稳离子的质量数。

公开(公告)号：US4918070A

公开(公告)日：1990-04-17

申请号：US161100

申请日：1988-02-26

申请人： Susumu Nakagawa ,  Hiroshi Fukatsu ,  Yoshiaki Katoh ,  Satoshi Murase

发明人： Susumu Nakagawa ,  Hiroshi Fukatsu ,  Yoshiaki Katoh ,  Satoshi Murase

IPC分类号： A61K31/545 ,  C07D501/26 ,  C07D501/59

CPC分类号： C07D501/59

摘要： A cephalosporin derivative having the formula: ##STR1## wherein R.sup.1 is a substituted amino group, X is an alkylene group, R.sup.2 is an aryl or heterocyclic group which may be substituted and R.sup.3 is a hydrogen atom, a negative charge or a residue of an ester which can form a pharmaceutically acceptable ester hydrolyzable in a living body; or a pharmaceutically acceptable salt thereof.

公开(公告)号：US4561147A

公开(公告)日：1985-12-31

申请号：US564739

申请日：1983-12-22

申请人： Yoshiaki Katoh ,  Hiroshi Inuzuka

发明人： Yoshiaki Katoh ,  Hiroshi Inuzuka

IPC分类号： E05D5/12 ,  E05D7/00

CPC分类号： E05D5/12 ,  E05D7/00 ,  E05D5/128 ,  E05Y2900/132 ,  Y10T16/538 ,  Y10T16/553

摘要： A door hinge of the type comprising a first metal plate having one vertical side edge formed integral with a pin and a second metal piece having one vertical side edge formed integral with a second knuckle cylinder into which is fitted the pin. A load plug is slideably fitted into the second knuckle cylinder for engagement with the upper end of the pin and the second knuckle cylinder is formed with an engaging portion for preventing the load plug from being displaced from a predetermined position. A compression spring means is loaded in the second knuckle cylinder above the load plug so as to press the load plug against the engaging portion, whereby a load applied axially to the pin is carried by the compression spring means through the load plug. When the upper or lower side edge of the door interferes with a gate frame due to an earthquake or the like, the first and second plate metals are caused to move toward or away from each other so that the interference between the door and the gate frame is eliminated and the door is moved upwardly or downwardly relative to the gate frame. Therefore even when the gate frame is distorted, the door can be positively opened.

摘要翻译： 一种门铰链，其类型包括具有与销一体形成的一个垂直侧边缘的第一金属板和具有与第二转向节缸一体形成的一个垂直侧边缘的第二金属件，所述第二转向节安装到销中。 负载塞可滑动地装配到第二关节缸中，用于与销的上端接合，并且第二转向节缸形成有用于防止负载插塞从预定位置移位的接合部分。 压缩弹簧装置装载在负载塞上方的第二转向节缸中，以将负载塞压靠在接合部分上，由此轴向施加到销的负载由压缩弹簧装置通过负载塞承载。 当门的上侧或下侧边缘由于地震等而与门框干涉时，使第一和第二板金属彼此移动或移开，使得门与门框之间的干涉 并且门相对于门框架向上或向下移动。 因此，即使门框失真，也可以正确打开门。

公开(公告)号：US5049665A

公开(公告)日：1991-09-17

申请号：US414389

申请日：1989-09-29

申请人： Susumu Nakagawa ,  Hiroshi Fukatsu ,  Yoshiaki Katoh ,  Satoshi Murase

发明人： Susumu Nakagawa ,  Hiroshi Fukatsu ,  Yoshiaki Katoh ,  Satoshi Murase

IPC分类号： A61K31/545 ,  C07D501/26 ,  C07D501/59

CPC分类号： C07D501/59

摘要： A cephalosporin derivative having the formula: ##STR1## wherein R.sup.1 is a substituted amino group, X is an alkylene group, R.sup.2 is an aryl or heterocyclic group which may be substituted and R.sup.3 is a hydrogen atom, a negative charge or a residue of an ester which can form a pharmaceutically acceptable ester hydrolyzable in a living body; or a pharmaceutically acceptable salt thereof.