公开(公告)号：US08990490B2

公开(公告)日：2015-03-24

申请号：US13686643

申请日：2012-11-27

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Vidhya Thyagarajan ,  Prasanna Kole ,  Gidda Reddy Gangula

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/0646 ,  G06F13/16 ,  G06F13/1642 ,  Y02D10/13 ,  Y02D10/14

Abstract: Memory controller concepts are disclosed in which hardware resources of a memory controller can be re-used or re-configured to accommodate various different memory configurations. The memory configuration may be stored in mode register bits (228), settable by a host or operating system. By re-configuring or reallocating certain resources of a memory controller, for example command logic blocks (A, B, C, D in FIG. 1A), a single controller design can be used to interface efficiently with a variety of different memory components. Command logic blocks that support N×M memory ranks, for example, can be reconfigured to support N ranks and M threads for multi-threaded memories (FIG. 1A). Data buffer (232, 254) depth can be extended by reconfiguring the buffers responsive to the mode register bits (228). Request buffers can be shared across command logic blocks, for example to increase the request buffer depth (FIG. 3A). Unused circuits can be powered down to save power consumption (FIG. 4A).

Abstract translation: 公开了存储器控制器概念，其中可以重新使用或重新配置存储器控制器的硬件资源以适应各种不同的存储器配置。 存储器配置可以存储在由主机或操作系统设置的模式寄存器位（228）中。 通过重新配置或重新分配存储器控制器的某些资源，例如命令逻辑块（图1A中的A，B，C，D），可以使用单个控制器设计来有效地与各种不同的存储器组件进行接口。 例如，支持N×M内存等级的命令逻辑块可被重新配置为支持用于多线程存储器的N个队列和M个线程（图1A）。 可以通过根据模式寄存器位重新配置缓冲区来扩展数据缓冲区（232,254）的深度（228）。 请求缓冲区可以在命令逻辑块之间共享，例如增加请求缓冲区深度（图3A）。 未使用的电路可以掉电以节省功耗（图4A）。

公开(公告)号：US20140029331A1

公开(公告)日：2014-01-30

申请号：US13936777

申请日：2013-07-08

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Renu Rangnekar

IPC: G11C11/4063

CPC classification number: G11C11/4063 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

Abstract: An integrated circuit memory device is disclosed. The memory device includes a memory core having a timing input to receive a clock signal. An interface couples to the memory core. The interface includes a receiver to receive a serial stream of write data bits and a sampler clocked by a strobe signal to generate serialized write data. The interface also includes a deserializer and control logic. The deserializer includes an input to receive the serialized write data and an output to generate parallel data responsive to a control signal generated by the control logic. In a first mode of operation, the control logic generates the control signal with respect to the clock signal. In a second mode of operation, the control logic generates the control signal with respect to the strobe signal.

Abstract translation: 公开了一种集成电路存储器件。 存储器件包括具有用于接收时钟信号的定时输入的存储器芯。 接口耦合到内存核心。 该接口包括用于接收写入数据位的串行流的接收器和由选通信号计时的采样器，以产生串行化写入数据。 该接口还包括解串器和控制逻辑。 解串器包括用于接收串行写入数据的输入端和响应于由控制逻辑产生的控制信号产生并行数据的输出端。 在第一操作模式中，控制逻辑产生相对于时钟信号的控制信号。 在第二操作模式中，控制逻辑产生关于选通信号的控制信号。