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81.发明授权公开(公告)号：US07143387B2
公开(公告)日：2006-11-28
申请号：US10651187
申请日：2003-08-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods, data processing systems, and program products are disclosed that support the definition and accessing of links indicating a relationship between configuration construct instances, such as Dial and Dial group instances, within a digital design. According to one method, first and second latches within the digital design are specified in at least one HDL statement within one or more HDL files representing the digital design. In the one or more HDL files, a first configuration construct instance referencing the first latch and a second configuration construct instance referencing the second latch are also defined. The first and second configuration construct instances provide interfaces through which values of the first and second latches can be accessed. In addition, a link indicating a relationship between the first and second configuration construct instances is also defined within the one or more HDL files.
摘要翻译： 公开了支持在数字设计中指示配置构造实例（例如拨号和拨号组实例）之间的关系的链接的定义和访问的方法，数据处理系统和程序产品。 根据一种方法，数字设计中的第一和第二锁存器在表示数字设计的一个或多个HDL文件内的至少一个HDL语句中被指定。 在一个或多个HDL文件中，还定义了引用第一锁存器的第一配置结构实例和引用第二锁存器的第二配置结构实例。 第一和第二配置构造实例提供可以访问第一和第二锁存器的值的接口。 此外，还在一个或多个HDL文件内定义指示第一和第二配置构造实例之间的关系的链接。
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公开(公告)号：US07143019B2
公开(公告)日：2006-11-28
申请号：US09997802
申请日：2001-11-30
CPC分类号： G01R31/318357 , G01R31/318314 , G06F17/5022
摘要： A method and system for associating instrumentation data with a simulation model within a batch simulation farm in which a simulation client communicates with an instrumentation server to process simulation data with respect to the simulation model. In accordance with the method of the present invention, an instrumentation eventlist is delivered from the simulation client to the instrumentation server. The eventlist contains instrumentation event information for the simulation model. Next, within the instrumentation server, a digital signature is computed that uniquely identifies contents of the instrumentation eventlist as being associated with the simulation model. Responsive to receiving simulation data from the simulation client, the digital signature is utilized to associate the simulation data with the simulation model.
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83.发明授权Method, system and program product for specifying a configuration for multiple signal or dial instances in a digital system 失效用于指定数字系统中多个信号或拨号实例的配置的方法，系统和程序产品公开(公告)号：US07134098B2
公开(公告)日：2006-11-07
申请号：US10425051
申请日：2003-04-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A digital system includes a plurality of hierarchically arranged design entity instantiations including a first entity instantiation containing second and third instantiations of the same design entity. Each of the instantiations contains a respective instance of a configurable entity having a plurality of possible configuration values that each corresponds to a different configuration of a functional portion of the digital system. A configuration specification for the digital system is received including a Dial containing a mapping between each of a plurality of possible Dial input values and a respective one of a plurality of configuration values. The configuration specification generically refers to the design entity. In response to receipt of the configuration specification, both instance of the configurable entity are automatically located. In response to the instances of the configurable entity, an association between the mapping and each of the instances of the configurable entity is automatically created.
摘要翻译： 数字系统包括多个分层布置的设计实体实例，其包括包含相同设计实体的第二和第三实例的第一实体实例。 每个实例包含具有多个可能配置值的可配置实体的相应实例，每个配置值对应于数字系统的功能部分的不同配置。 接收数字系统的配置规范，包括包含多个可能拨号输入值中的每一个与多个配置值中的相应一个之间的映射的拨号。 配置规范一般指设计实体。 响应于接收到配置规范，可配置实体的两个实例都被自动定位。 响应于可配置实体的实例，映射与可配置实体的每个实例之间的关联被自动创建。
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84.发明授权Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs 失效提供配置规范语言的方法，系统和程序产品，支持用于配置结构的任意映射功能公开(公告)号：US07096434B2
公开(公告)日：2006-08-22
申请号：US10749759
申请日：2003-12-31
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.
摘要翻译： 公开了一种将映射函数与由一个或多个硬件描述语言（HDL）文件定义的数字设计的配置结构相关联的方法。 根据该方法，在HDL文件中，在形成数字设计的至少一部分的设计实体内指定配置锁存器。 此外，指定了一个Dial，其定义了多个输入值中的每一个与多个不同输出值中的相应的一个之间的关系。 HDL文件还包括一个语句，用于与配置锁存器相关联地实例化Dial的实例，使得在配置锁存器中包含的值与Dial的实例的输入值之间存在一一对应的对应关系。 HDL文件还包括将Dial与将映射功能相关联的语句，该映射函数将选择的变换应用于从Dial的实例读取或写入的值。
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85.发明授权公开(公告)号：US06590929B1
公开(公告)日：2003-07-08
申请号：US09328300
申请日：1999-06-08
IPC分类号： H04B1700
CPC分类号： G01R31/318547 , G01R31/31813 , G01R31/318566
摘要： A system for controllable run-time verification of operations in a logic structure of a digital system. The system comprises a controllable bit stream generator which produces a controlled bit stream output. The controlled bit stream output corresponds to a bit sequence which instantiates a verification of operations within the logic structure. The system also comprises means for coupling the controlled bit stream output to the logic structure to verify the operations of the logic structure.
摘要翻译： 一种用于数字系统的逻辑结构中的操作的可控运行时验证的系统。 该系统包括产生受控比特流输出的可控比特流发生器。 受控比特流输出对应于实例化逻辑结构内的操作验证的比特序列。 该系统还包括用于将受控比特流输出耦合到逻辑结构以验证逻辑结构的操作的装置。
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公开(公告)号：US06212491B1
公开(公告)日：2001-04-03
申请号：US09190862
申请日：1998-11-09
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for automatically adjusting counting rates of instrumentation within a simulation model of a digital circuit design, during simulation of said digital circuit design. According to the present invention a design entity that will be incorporated into a simulation model of a digital circuit design is described utilizing a hardware description language. The design entity operates, during simulation, in conformity with a design cycle that consists of a multiple of a simulator cycle. Next, an instrumentation entity is described utilizing the same hardware description language. The description of the instrumentation entity contains logic to detect occurrences of a count event that occurs in conformity with the design cycle during simulation. Thereafter, an instrumentation logic block associated with the instrumentation entity is automatically generated and utilized for counting occurrences of the count event detected by the instrumentation entity. Finally, the design cycle is encoded within the instrumentation entity, such that the output logic block is automatically adjusted to count in conformity with the design cycle.
摘要翻译： 公开了一种在所述数字电路设计的仿真期间利用硬件描述语言的表现性来自动调整数字电路设计的仿真模型中的仪表的计数率的方法和系统。 根据本发明，将使用硬件描述语言描述将被并入数字电路设计的仿真模型中的设计实体。 设计实体在模拟期间运行，符合由模拟器周期的倍数组成的设计周期。 接下来，使用相同的硬件描述语言来描述仪器实体。 仪表实体的描述包含检测在仿真期间符合设计周期发生的计数事件发生的逻辑。 此后，与仪器实体相关联的仪表逻辑块被自动生成并用于计数由仪器实体检测到的计数事件的发生。 最后，设计周期在仪器实体内进行编码，使输出逻辑块自动调整为符合设计周期。
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公开(公告)号：US06202042B1
公开(公告)日：2001-03-13
申请号：US09190863
申请日：1998-11-09
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and system are disclosed that utilize the expressiveness of hardware description languages for providing comprehensive runtime monitoring during hardware accelerated simulation of a digital circuit design. According to the present invention a design entity forming part of a digital circuit design that will be translated and assembled into a simulation executable model, is described utilizing a hardware description language. Next, an instrumentation entity designed to send a failure signal in response to detecting an occurrence of a failure event within the simulation executable model is described utilizing the same hardware description language. Thereafter, a simulation test is initiated on the simulation executable model utilizing a hardware simulator. Finally, during the simulation test, and in response to receiving a failure signal from the instrumentation entity, the simulation test is terminated such that the failure event may be efficiently identified and diagnosed.
摘要翻译： 公开了一种方法和系统，其利用硬件描述语言的表现性来在数字电路设计的硬件加速仿真期间提供全面的运行时监视。 根据本发明，利用硬件描述语言描述形成将被翻译并组装成模拟可执行模型的数字电路设计的一部分的设计实体。 接下来，使用相同的硬件描述语言来描述被设计成响应于检测模拟可执行模型内的故障事件的发生而发送故障信号的仪表实体。 此后，利用硬件模拟器对仿真可执行模型进行模拟测试。 最后，在仿真测试期间，并且响应于接收到来自仪器实体的故障信号，模拟测试被终止，从而可以有效地识别和诊断故障事件。
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88.发明授权Annotating system traces with control program information and presenting annotated system traces 失效用控制程序信息注释系统跟踪，并显示注释的系统跟踪公开(公告)号：US08296740B2
公开(公告)日：2012-10-23
申请号：US12057829
申请日：2008-03-28
IPC分类号： G06F9/44
CPC分类号： G06F11/3664 , G06F11/3636
摘要： The signal state that a signal of interest within a system under test has during each of a plurality of cycles of operation of the system under test is stored in a trace file. In association with the signal state, information regarding a requested access to the signal state by a control program during a particular cycle among the plurality of cycles is also stored. From the trace files a presentation is generated that presents, for at least a signal of interest within the system under test, a plurality of signal state indications, each indicating a respective state that the signal had during a one of a plurality of cycles of operation of the system under test. The presentation also indicates, in a graphically distinctive manner, at least one cycle of operation during which a control program requested access to a state of the signal, so that the influence of the control program on the state of the system under test is visually apparent.
摘要翻译： 被测系统中感兴趣的信号在被测系统的多个操作周期中的每一个期间的信号状态被存储在跟踪文件中。 与信号状态相关联，还存储关于在多个周期中的特定周期期间由控制程序请求的访问信号状态的信息。 从跟踪文件中产生一个演示文稿，对于至少在被测系统内感兴趣的信号，呈现多个信号状态指示，每个信号状态指示各自表示信号在多个操作周期之一中具有的状态 的被测系统。 演示文稿还以图形上独特的方式指示至少一个操作周期，在该周期期间控制程序请求访问信号的状态，使得控制程序对被测系统的状态的影响在视觉上是明显的 。
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公开(公告)号：US07921389B2
公开(公告)日：2011-04-05
申请号：US12146208
申请日：2008-06-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/505
摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.
摘要翻译： 在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。 设计实体逻辑地包含第一和第二锁存器，每个锁存器具有相应的多个不同的可能锁存值。 利用一个或多个语句，第一拨号实例与第一锁存器相关联，并且第二拨号实例与第二锁存器相关联。 因此，第一拨号实例的设置控制多个不同可能值中的哪一个加载到第一锁存器中，并且第二拨号实例的设置控制多个不同可能值中的哪一个加载到第二锁存器中。 通过语句，寄存器实例同时与第一和第二锁存器相关联，使得寄存器实例的设置控制加载在第一和第二锁存器中的锁存值。
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90.发明授权公开(公告)号：US07895558B2
公开(公告)日：2011-02-22
申请号：US12110047
申请日：2008-04-25
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of the digital design. In addition, a Dial is specified that defines a relationship between each of a plurality of input values and a respective one of a plurality of different output values. The HDL files also include a statement that instantiates an instance of the Dial in association with the configuration latch such that a one-to-one correspondence exists between a value contained within the configuration latch and an input value of the instance of the Dial. The HDL files further include a statement associating the Dial with a mapping function that applies a selected transformation to values read from or written to the instance of the Dial.
摘要翻译： 公开了一种将映射函数与由一个或多个硬件描述语言（HDL）文件定义的数字设计的配置结构相关联的方法。 根据该方法，在HDL文件中，在形成数字设计的至少一部分的设计实体内指定配置锁存器。 此外，指定了一个Dial，其定义了多个输入值中的每一个与多个不同输出值中的相应的一个之间的关系。 HDL文件还包括一个语句，用于与配置锁存器相关联地实例化Dial的实例，使得在配置锁存器中包含的值与Dial的实例的输入值之间存在一一对应的对应关系。 HDL文件还包括将Dial与将映射功能相关联的语句，该映射函数将选择的变换应用于从Dial的实例读取或写入的值。
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