公开(公告)号：US10665195B2

公开(公告)日：2020-05-26

申请号：US16176016

申请日：2018-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  G11C19/28 ,  G11C19/18 ,  H01L27/12

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

公开(公告)号：US20200150473A1

公开(公告)日：2020-05-14

申请号：US16732445

申请日：2020-01-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Hiroyuki Miyake

IPC: G02F1/1368 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/36 ,  H01L27/12 ,  G02F1/1362 ,  H01L27/32

Abstract: An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

公开(公告)号：US10593274B2

公开(公告)日：2020-03-17

申请号：US15700825

申请日：2017-09-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/30 ,  G09G3/36 ,  G09G3/20 ,  H03K17/04

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

公开(公告)号：US10527902B2

公开(公告)日：2020-01-07

申请号：US16100261

申请日：2018-08-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Hiroyuki Miyake

IPC: G02F1/1368 ,  G09G3/3233 ,  H01L27/12 ,  G02F1/1362 ,  H01L27/32 ,  G09G3/3266 ,  G09G3/36 ,  G09G3/20 ,  G09G3/3275 ,  G09G3/34 ,  H01L29/423 ,  H01L27/15

Abstract: An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

公开(公告)号：US10460690B2

公开(公告)日：2019-10-29

申请号：US15434142

申请日：2017-02-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G09G3/36 ,  G09G3/20 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

Abstract: A driver circuit includes a circuit 200, a transistor 101_1, and a transistor 101_2. A signal is selectively input from the circuit 200 to a gate of the transistor 101_1 and the transistor 101_2, so that the transistor 101_1 and the transistor 101_2 are controlled to be on or off. The transistor 101_1 and the transistor 101_2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.

公开(公告)号：US20190280022A1

公开(公告)日：2019-09-12

申请号：US16420430

申请日：2019-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H01L27/12 ,  H01L27/06 ,  G09G3/3266 ,  H01L27/32 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1368 ,  G09G3/36 ,  G02F1/1362 ,  G09G3/34 ,  G11C19/28

Abstract: It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

公开(公告)号：US20190206354A1

公开(公告)日：2019-07-04

申请号：US16176016

申请日：2018-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  G11C19/28 ,  G11C19/18 ,  H01L27/12

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

公开(公告)号：US10325932B2

公开(公告)日：2019-06-18

申请号：US15222378

申请日：2016-07-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/00 ,  H01L27/12 ,  G02F1/1362 ,  G09G3/20 ,  G09G3/325 ,  G09G3/36 ,  G11C19/28 ,  H03K19/003 ,  H03K3/356 ,  G09G3/3266 ,  G09G3/3258

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

公开(公告)号：US10304872B2

公开(公告)日：2019-05-28

申请号：US15795321

申请日：2017-10-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H03B1/00 ,  H03K3/00 ,  H01L27/12 ,  G09G3/14 ,  G09G3/32 ,  G09G3/36 ,  G11C19/00 ,  H03K17/687 ,  H01L29/786

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

公开(公告)号：US10304868B2

公开(公告)日：2019-05-28

申请号：US15954699

申请日：2018-04-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H01L27/12 ,  G09G3/36 ,  G09G3/20 ,  H01L21/84 ,  G02F1/1368 ,  H01L27/15 ,  G02F1/1362 ,  H01L27/32 ,  H01L29/786 ,  G02F1/133

Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.