公开(公告)号：US11309361B2

公开(公告)日：2022-04-19

申请号：US16725248

申请日：2019-12-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kang Moon Jo ,  Dong Woo Kim ,  Sung Jae Moon ,  Jun Hyun Park ,  An Su Lee

IPC: H01L29/08 ,  H01L27/32

Abstract: A display device includes a substrate including a plurality of light-emitting devices, a first color filter, a second color filter, and a third color filter that overlap one of the light-emitting devices, and a first color converting layer that overlaps the first color filter, a second color converting layer that overlaps the second color filter, and a transmission layer that overlaps the third color filter. A plurality of the first color filters, a plurality of the second color filters, and a plurality of the third color filters are arranged in a first direction. A gap between adjacent second color filters in a second direction overlaps the first color filter in the first direction.

公开(公告)号：US20220101777A1

公开(公告)日：2022-03-31

申请号：US17323213

申请日：2021-05-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hyun Joon Kim ,  Jang Mi Kang ,  Hae Min Kim ,  Jun Hyun Park ,  Min Jae Jeong ,  Ki Hyun Pyo

IPC: G09G3/32

Abstract: A display device according to an embodiment of the present disclosure includes pixels connected to a first scan line, a second scan line, a third scan line, a data line, a first emission control line, and a second emission control line. Each of the pixels includes a light emitting element; a first transistor connected between a first node connected to a first power source and a second electrode connected to a second node connected to an anode of the light emitting element, and including a gate electrode connected to a third node; a second transistor connected between the data line and a fourth node and including a gate electrode connected to the first scan line; a first capacitor connected between the second node and a fifth node; a second capacitor connected between the fourth node and the fifth node; a fourth transistor connected between the third node and the fifth node, and including a gate electrode connected to the second scan line; and a sixth transistor connected between the third node and the fourth node, and including a gate electrode connected to the first emission control line.

公开(公告)号：US11270648B2

公开(公告)日：2022-03-08

申请号：US16817694

申请日：2020-03-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung Jae Moon ,  Dong Woo Kim ,  Kang Moon Jo ,  Jun Hyun Park ,  An Su Lee

IPC: G09G3/3266 ,  H01L27/32 ,  G09G3/3291

Abstract: A display device includes a first conductive layer, a first insulation layer disposed on the first conductive layer, and active patterns disposed on the first insulation layer. The display device further includes a second conductive layer disposed on the active patterns and including a first gate electrode that overlaps a channel region of the active patterns and a driving gate electrode, a second insulation layer disposed on the second conductive layer, a third conductive layer including a capacitor electrode and at least one scan line disposed on the second insulation layer, a third insulation layer disposed on the third conductive layer, and an electrode layer including a first electrode disposed on the third insulation layer. The first electrode is connected to the capacitor electrode, the capacitor electrode overlaps the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.

公开(公告)号：US11238809B2

公开(公告)日：2022-02-01

申请号：US16901079

申请日：2020-06-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Hyun Park ,  Dong Woo Kim ,  An Su Lee ,  Kang Moon Jo

IPC: G09G3/3266 ,  G09G3/3225 ,  G09G3/3275

Abstract: A scan signal driver including: a plurality of stages for outputting scan signals and sensing signals, wherein a kth stage among the stages is connected to a kth scan signal line and a kth sensing signal line, and wherein the kth stage includes: a first output unit configured to output a scan clock signal input to a fit scan clock terminal to the kth scan signal line as a kth scan signal and to output a sensing clock signal input to a first sensing clock terminal to the kth sensing signal line as a k sensing signal when a pull-up node has a gate-on voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a kth carry signal to a carry output terminal when the pull-up node has the gate-on voltage.

公开(公告)号：US11201204B2

公开(公告)日：2021-12-14

申请号：US16596952

申请日：2019-10-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kang Moon Jo ,  Dong Woo Kim ,  Sung Jae Moon ,  Jun Hyun Park ,  An Su Lee

IPC: H01L27/32 ,  H01L51/52 ,  H01L27/12

Abstract: A display device including: a substrate; an active layer disposed on the substrate and including active patterns; a first conductive layer disposed on the active layer; a second conductive layer disposed on the first conductive layer and including a data line; a third conductive layer disposed on the second conductive layer; and a light-emitting element disposed on the third conductive layer, wherein the first conductive layer includes a scan line, a first voltage line, and a second voltage line, the third conductive layer includes a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction.

公开(公告)号：US10991305B2

公开(公告)日：2021-04-27

申请号：US16264199

申请日：2019-01-31

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun Park ,  Cheol Gon Lee ,  Yang Hwa Choi

IPC: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266

Abstract: An organic light emitting (OLE) display device includes pixels connected to scan lines (SLs), data lines (DLs), and a first control line (FCL) commonly connected to the pixels. Each pixel includes: an OLE diode connected between a first power source (PS) and a second PS; a first transistor (TFT1) connected between the first PS and the OLE diode, a gate electrode (GE) of the TFT1 being connected to a first node (N1); a second transistor (TFT2) connected between the N1 and a second node (N2), a GE of the TFT2 being connected to a SL; a third transistor (TFT3) connected between the N2 and a third node (N3), the N3 being connected between the TFT1 and the OLED, a GE of the TFT3 being connected to the FCL; a first capacitor connected between the first PS and the N1; and a second capacitor connected between the N2 and a DL.

公开(公告)号：US20210082353A1

公开(公告)日：2021-03-18

申请号：US17093876

申请日：2020-11-10

Applicant: Samsung Display Co. Ltd.

Inventor： Jun Hyun Park ,  Sun Kwang Kim ,  Young Wan Seo ,  Cheol Gon Lee ,  Yang Hwa Choi

IPC: G09G3/3291 ,  G09G3/3258 ,  G09G3/3233 ,  G09G3/3266

Abstract: A display device includes a data line to which a data voltage is applied, a first driving voltage line to which a first driving voltage is applied, a second driving voltage line to which a second driving voltage is applied, and a pixel connected to the first and second driving voltage lines. The pixel includes a first transistor to control a driving current according to a voltage applied to a first node, a light emitting element between the first transistor and the first driving voltage line, and a capacitor between the first node and the second driving voltage line. The first driving voltage has a first high-level voltage during a first initialization period, the first driving voltage has a first mid-level voltage lower than the first high level voltage during a threshold-voltage-storage period, and the first driving voltage has a first low-level voltage during a second initialization period.

公开(公告)号：US20200235183A1

公开(公告)日：2020-07-23

申请号：US16735962

申请日：2020-01-07

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Hyun Park ,  Dong Woo Kim ,  Sung Jae Moon ,  Kang Moon Jo

IPC: H01L27/32

Abstract: A display device having high resolution includes: a first conductive layer, an active pattern, second to fourth conductive layers, and a pixel electrode sequentially formed on a substrate, with first to fourth insulating layers separately interposed therebetween, the first conductive layer including a lower pattern, the active pattern including a source region, a channel region, and a drain region, the second conductive layer including a gate electrode overlapping the channel region and a driving gate electrode connected to the gate electrode, the third conductive layer including a capacitor electrode overlapping the driving gate electrode, the fourth conductive layer including an additional capacitor electrode overlapping the capacitor electrode. The driving gate electrode and the capacitor electrode may form a storage capacitor, the pixel electrode and the additional capacitor electrode may form a first additional capacitor, and the capacitor electrode and the additional capacitor electrode may form a second additional capacitor.

公开(公告)号：US10121434B2

公开(公告)日：2018-11-06

申请号：US15042029

申请日：2016-02-11

Applicant: Samsung Display Co., Ltd

Inventor： Jun Hyun Park ,  Sung Hwan Kim ,  Se Young Song ,  Kyoung Ju Shin ,  Jae Keun Lim

IPC: G11C19/00 ,  G09G3/36 ,  G09G3/20 ,  G11C19/28 ,  H03K17/687

Abstract: There is provided a stage circuit capable of minimizing a mounting area. The stage circuit includes: an output unit configured to supply a voltage of a first node, an i-th (i is a natural number) carry signal, and to supply an i-th scan signal in response to the voltage of the first node, a voltage of a second node, and a first clock signal, a controller configured to control the voltage of the second node in response to the first clock signal; a pull-up unit configured to control the voltage of the first node in response to a carry signal of a previous stage and a voltage of a first node of the previous stage, and a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and a carry signal of a next stage.

公开(公告)号：US10079598B2

公开(公告)日：2018-09-18

申请号：US15048979

申请日：2016-02-19

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun Park ,  Sung Hwan Kim ,  Se Young Song ,  Kyoung Ju Shin

IPC: G11C19/28 ,  G09G3/20 ,  G11C19/18 ,  H03K17/687

CPC classification number: H03K17/6871 ,  G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving circuit includes: a plurality of stages configured to output a plurality of gate signals, wherein an Nth stage of the plurality of stages includes: an output pull-up unit including a control electrode connected to a first node, wherein the output pull-up unit is configured to increase an electric potential at the first node and is further configured to receive a clock signal and to output a gate signal of the Nth stage; a control node pull-up unit configured to charge the first node according to an (N−1)th control signal and an (N−2)th control signal; a control node pull-down unit configured to discharge a voltage of the first node as a first low voltage according to an (N+1)th control signal; and an output pull-down unit configured to discharge a gate signal of the Nth stage as the first low voltage according to the (N+1)th control signal.