公开(公告)号：US10964643B2

公开(公告)日：2021-03-30

申请号：US16696759

申请日：2019-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim Suk ,  Seokhyun Lee

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/14 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L21/683

Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.

公开(公告)号：US10923407B2

公开(公告)日：2021-02-16

申请号：US15630934

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek ,  Seokhyun Lee

IPC: H01L21/66 ,  H01L23/485 ,  H01L21/822 ,  H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

公开(公告)号：US20200328175A1

公开(公告)日：2020-10-15

申请号：US16914384

申请日：2020-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Ji Min ,  Seokhyun Lee ,  Jongyoun Kim ,  Kyoung Lim Suk ,  SeokWon Lee

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/683

Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.

公开(公告)号：US10541201B2

公开(公告)日：2020-01-21

申请号：US16136622

申请日：2018-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyung Suk Oh

IPC: H01L29/80 ,  H01L31/0288 ,  H01L31/112 ,  H01L23/522 ,  H01L23/498 ,  H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a first surface of the package substrate, a connection substrate on the package substrate and spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the semiconductor chip and the package substrate and electrically connecting the semiconductor chip to the package substrate, a plurality of second connecting elements between the connection substrate and the package substrate and electrically connecting the connection substrate to package substrate, a mold layer encapsulating the semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the semiconductor chip and electrically connected to a corresponding one of the plurality of conductive connection structures may be provided.