公开(公告)号：US09099460B2

公开(公告)日：2015-08-04

申请号：US14466207

申请日：2014-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/552 ,  H01L23/28 ,  H01L23/31 ,  H01L23/00 ,  H01L25/03 ,  H01L25/18 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US08823171B2

公开(公告)日：2014-09-02

申请号：US13889343

申请日：2013-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho

IPC: H01L23/498 ,  H01L25/065

CPC classification number: H01L23/49811 ,  H01L23/49822 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161

Abstract: Provided are a semiconductor package, a semiconductor device provided with the same, and a method of fabricating the same. The semiconductor package may include a package substrate including a central region and a peripheral region, a first semiconductor chip provided on the package substrate, a first connection pattern provided on the central region of the package substrate to connect the package substrate electrically to the first semiconductor chip, at least one second semiconductor chip provided on the peripheral region of the package substrate and between the package substrate and the first semiconductor chip, and a second connection pattern provided on the peripheral region of the package substrate to connect the first semiconductor chip electrically to the second semiconductor chip.

Abstract translation: 提供一种半导体封装，具备该半导体封装的半导体器件及其制造方法。 半导体封装可以包括包括中心区域和外围区域的封装衬底，设置在封装衬底上的第一半导体芯片，设置在封装衬底的中心区域上的第一连接图案，以将封装衬底电连接到第一半导体 芯片，设置在封装基板的周边区域和封装基板与第一半导体芯片之间的至少一个第二半导体芯片，以及设置在封装基板的外围区域上的第二连接图案，以将第一半导体芯片电连接到 第二个半导体芯片。

公开(公告)号：US10923407B2

公开(公告)日：2021-02-16

申请号：US15630934

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek ,  Seokhyun Lee

IPC: H01L21/66 ,  H01L23/485 ,  H01L21/822 ,  H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

公开(公告)号：US09570411B2

公开(公告)日：2017-02-14

申请号：US14920927

申请日：2015-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gyu Baek ,  Young-Min Lee ,  Yun-Rae Cho ,  Sun-Dae Kim

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05085 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/08113 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection.

Abstract translation: 可用于半导体器件的焊盘结构可以包括绝缘层图案结构，插头和焊盘。 绝缘层图案结构具有插塞孔和至少一个通孔。 插头形成在插头孔中。 衬垫形成在绝缘层图案结构上。 垫与插头电连接，具有下表面和不平的上表面。 下表面包括插入通孔的突出部分。 不平坦的上表面包括凹部和升高部分，以提供高粗糙度和牢固的连接。

公开(公告)号：US10916509B2

公开(公告)日：2021-02-09

申请号：US16530993

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Sundae Kim ,  Hyunggil Baek ,  Namgyu Baek ,  Seunghun Shin ,  Donghoon Won

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/02 ,  H01L23/58

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US20190164915A1

公开(公告)日：2019-05-30

申请号：US16024309

申请日：2018-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sundae Kim ,  Yun-Rae Cho ,  Namgyu Baek

IPC: H01L23/58 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a substrate including a first region and a second region at least partially surrounding the first region in a plan view. A protection pattern is disposed on the second region of the substrate and at least partially surrounds the first region of the substrate in the plan view. A protection trench overlaps the protection pattern and at least partially surrounds the first region of the substrate in the plan view, along the protection pattern. A width of the protection trench is different from a width of the protection pattern.

公开(公告)号：US20140363923A1

公开(公告)日：2014-12-11

申请号：US14466207

申请日：2014-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L25/00 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US08890294B2

公开(公告)日：2014-11-18

申请号：US13771609

申请日：2013-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Tae-Hoon Kim ,  Ho-Geon Song ,  Seok-Won Lee

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/552 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract translation: 为了制造堆叠半导体封装，板模具覆盖第一半导体。 板模具包括第一面和与第一面相对的第二面。 第一半导体的有源表面面向第二面。 第一开口从第二表面形成在板模具中。 第一开口设置在第一半导体上。 第二开口从第一表面穿透板模。 导电金属层使用化学镀方法填充第一和第二开口。 多个半导体器件堆叠在基板模具的第一面上。

公开(公告)号：US20240088082A1

公开(公告)日：2024-03-14

申请号：US18229446

申请日：2023-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho Cha ,  Yun-Rae Cho

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L23/5228 ,  H01L23/544 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17133 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/3511

Abstract: A semiconductor package, including a substrate extending in first direction and a second direction intersecting the first direction and including a solder resist layer having an open area thereon; a semiconductor chip on the substrate in a third direction, the third direction intersecting the first direction and the second direction, a first surface of the semiconductor chip facing the substrate; and a bump structure in contact with a first connection pad on the open area and a second connection pad on the first surface of the semiconductor chip, and configured to connect the substrate to the semiconductor chip, wherein the open area includes a first area and a second area disposed in a peripheral part of the first area, and wherein a length of the first area in the first direction is greater than a length of the second area in the first direction.

公开(公告)号：US10950586B2

公开(公告)日：2021-03-16

申请号：US16437595

申请日：2019-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae Cho

IPC: H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of the package substrate. The solder bump includes a core portion and a peripheral portion encapsulating the core portion. The peripheral portion includes a first segment with a first melting point and a second segment with a second melting point that is less than the first melting point.