公开(公告)号：US12014975B2

公开(公告)日：2024-06-18

申请号：US17453243

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegwon Jang ,  Kyoung Lim Suk ,  Minjun Bae

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/04 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/16227

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an insulating layer, and first, second, and third redistribution patterns disposed in the insulating layer. The first to third redistribution patterns are sequentially stacked in an upward direction and are electrically connected to each other. Each of the first to third redistribution patterns includes a wire portion that extends parallel to the top surface of the redistribution substrate. Each of the first and third redistribution patterns further includes a via portion that extends from the wire portion in a direction perpendicular to the top surface of the redistribution substrate. The second redistribution pattern furthers include first fine wire patterns that are less wide than the wire portion of the second redistribution pattern.

公开(公告)号：US11887931B2

公开(公告)日：2024-01-30

申请号：US17213506

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung Song ,  Kyoung Lim Suk ,  Jaegwon Jang ,  Wonkyoung Choi

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L27/08 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/3114 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.

公开(公告)号：US10522471B2

公开(公告)日：2019-12-31

申请号：US16010872

申请日：2018-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim Suk ,  Seokhyun Lee

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/14 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L23/498

Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.

公开(公告)号：US11869775B2

公开(公告)日：2024-01-09

申请号：US18169161

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/485 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/73 ,  H01L21/60 ,  H01L2224/023 ,  H01L2224/0508 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US20230197469A1

公开(公告)日：2023-06-22

申请号：US18169161

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/485 ,  H01L21/60

CPC classification number: H01L21/563 ,  H01L24/73 ,  H01L24/13 ,  H01L24/05 ,  H01L23/49816 ,  H01L23/485 ,  H01L2224/05548 ,  H01L2224/05022 ,  H01L2924/15311 ,  H01L21/60 ,  H01L2224/13024 ,  H01L2224/0508 ,  H01L2224/73204 ,  H01L2224/023

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US20230085930A1

公开(公告)日：2023-03-23

申请号：US18060853

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US11348876B2

公开(公告)日：2022-05-31

申请号：US17130505

申请日：2020-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Seung-Kwan Ryu ,  Seokhyun Lee

IPC: H01L21/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L23/498

Abstract: A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

公开(公告)号：US11107700B2

公开(公告)日：2021-08-31

申请号：US16415272

申请日：2019-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim Suk

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: A method of fabricating a semiconductor package may include forming a lower re-distribution layer, forming a stack, bonding the stack to a portion of the lower re-distribution layer, stacking a semiconductor chip on a top surface of the lower re-distribution layer, and forming an upper re-distribution layer on the semiconductor chip and the stack.

公开(公告)号：US10546829B2

公开(公告)日：2020-01-28

申请号：US15867075

申请日：2018-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Ji Min ,  Seokhyun Lee ,  Jongyoun Kim ,  Kyoung Lim Suk ,  SeokWon Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/10

Abstract: A method of fabricating a semiconductor package including forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.

公开(公告)号：US12170251B2

公开(公告)日：2024-12-17

申请号：US17317368

申请日：2021-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate that has a first trench that extends through a top surface of the redistribution substrate, a first semiconductor chip on the redistribution substrate, a capacitor chip on a bottom surface of the first semiconductor chip, and an under-fill layer on the bottom surface of the first semiconductor chip. The redistribution substrate includes a plurality of dielectric layers vertically stacked, a plurality of redistribution patterns in each of the dielectric layers, and a plurality of dummy redistribution patterns in the first trench. The dummy redistribution patterns vertically overlap the first semiconductor chip. An uppermost surface of the dummy redistribution pattern is located at a level higher than a level of a bottom surface of the first trench.