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公开(公告)号：US20190206354A1
公开(公告)日：2019-07-04
申请号：US16176016
申请日：2018-10-31
发明人： Atsushi Umezaki
摘要： To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.
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公开(公告)号：US10325932B2
公开(公告)日：2019-06-18
申请号：US15222378
申请日：2016-07-28
发明人： Atsushi Umezaki
IPC分类号： G11C19/00 , H01L27/12 , G02F1/1362 , G09G3/20 , G09G3/325 , G09G3/36 , G11C19/28 , H03K19/003 , H03K3/356 , G09G3/3266 , G09G3/3258
摘要： An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.
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公开(公告)号：US10304872B2
公开(公告)日：2019-05-28
申请号：US15795321
申请日：2017-10-27
发明人： Atsushi Umezaki
IPC分类号： H03B1/00 , H03K3/00 , H01L27/12 , G09G3/14 , G09G3/32 , G09G3/36 , G11C19/00 , H03K17/687 , H01L29/786
摘要： Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.
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公开(公告)号：US10304868B2
公开(公告)日：2019-05-28
申请号：US15954699
申请日：2018-04-17
发明人： Atsushi Umezaki
IPC分类号： H01L27/12 , G09G3/36 , G09G3/20 , H01L21/84 , G02F1/1368 , H01L27/15 , G02F1/1362 , H01L27/32 , H01L29/786 , G02F1/133
摘要： To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.
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公开(公告)号：US10134775B2
公开(公告)日：2018-11-20
申请号：US15899472
申请日：2018-02-20
发明人： Atsushi Umezaki
IPC分类号： G09G3/36 , H01L27/12 , G11C19/28 , H01L27/105 , G02F1/1333 , G02F1/1368 , G09G3/3266 , G02F1/1362 , H01L29/423 , H01L29/786 , H01L27/13 , G02F1/1343 , G02F1/1345 , H01L27/32
摘要： By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.
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公开(公告)号：US10121435B2
公开(公告)日：2018-11-06
申请号：US15062265
申请日：2016-03-07
发明人： Atsushi Umezaki
摘要： To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.
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公开(公告)号：US10071904B2
公开(公告)日：2018-09-11
申请号：US14859681
申请日：2015-09-21
发明人： Atsushi Umezaki
IPC分类号： B81B7/00 , B81B3/00 , G09G3/34 , H03K19/003 , H03K19/00 , H03K19/0185 , H01L27/12
CPC分类号： B81B3/0083 , B81B7/008 , G09G3/3466 , G09G2300/08 , G09G2310/0262 , H01L27/1225 , H03K19/0013 , H03K19/00315 , H03K19/00384 , H03K19/018521
摘要： An object is to continuously apply voltage to a MEMS device using first to fifth or sixth transistors. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor. A gate of the first transistor is electrically connected to one of a source and a drain of the fifth transistor. A gate of the second transistor is electrically connected to the one of the source and the drain of the third transistor. A gate of the fourth transistor is electrically connected to the gate of the first transistor. The MEMS device is electrically connected to the one of the source and the drain of the first transistor.
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公开(公告)号：US09990894B2
公开(公告)日：2018-06-05
申请号：US15396862
申请日：2017-01-03
发明人： Hajime Kimura , Atsushi Umezaki
CPC分类号： G09G3/3648 , G09G3/2096 , G09G3/3677 , G09G3/3688 , G09G2300/0426 , G09G2300/0814 , G09G2300/0819 , G09G2320/0209 , G09G2320/0223 , G09G2320/043
摘要： A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.
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公开(公告)号：US09954010B2
公开(公告)日：2018-04-24
申请号：US15279575
申请日：2016-09-29
发明人： Atsushi Umezaki
IPC分类号： H01L25/00 , H03K19/094 , H01L27/12 , G09G3/36 , G09G3/20 , H01L21/84 , G02F1/1368 , H01L27/15 , G02F1/133 , G02F1/1362 , H01L27/32 , H01L29/786
CPC分类号： H01L27/124 , G02F1/13306 , G02F1/13624 , G02F1/136286 , G02F1/1368 , G02F2001/136245 , G09G3/20 , G09G3/3648 , G09G3/3677 , G09G2300/04 , G09G2300/08 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , H01L21/84 , H01L27/12 , H01L27/1222 , H01L27/1225 , H01L27/156 , H01L27/3262 , H01L27/3276 , H01L29/78696
摘要： To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.
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公开(公告)号：US09847352B2
公开(公告)日：2017-12-19
申请号：US15231851
申请日：2016-08-09
发明人： Hajime Kimura , Atsushi Umezaki
IPC分类号： H01L27/088 , H01L27/12 , H01L29/786 , G02F1/133 , G02F1/1339 , G02F1/1362 , G02F1/1368 , H01L29/417 , H01L29/423 , G11C19/28 , G02F1/1333 , G02F1/1343 , G09G3/36
CPC分类号： H01L27/1225 , G02F1/13306 , G02F1/133345 , G02F1/1339 , G02F1/134309 , G02F1/136213 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G09G3/3677 , G09G2310/0251 , G09G2310/08 , G09G2330/021 , G11C19/28 , H01L27/088 , H01L27/124 , H01L27/1244 , H01L27/1251 , H01L27/1255 , H01L27/127 , H01L27/1288 , H01L29/41733 , H01L29/42384 , H01L29/7869 , H01L29/78696
摘要： A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.
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