公开(公告)号：US20230168890A1

公开(公告)日：2023-06-01

申请号：US18097552

申请日：2023-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mujibur Rahman ,  Joseph Raymond Michael Zbiciak ,  Eric Biscondi ,  Peter Dent ,  Jelena Milanovic ,  Ashish Shrivastava

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3893 ,  G06F9/30021 ,  G06F9/30018 ,  G06F9/3001 ,  G06F9/30112

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

公开(公告)号：US20220261245A1

公开(公告)日：2022-08-18

申请号：US17738993

申请日：2022-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

公开(公告)号：US20220156072A1

公开(公告)日：2022-05-19

申请号：US17588416

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Soujanya Narnur ,  Timothy David Anderson ,  Mujibur Rahman ,  Duc Quang Bui

IPC: G06F9/30 ,  H03H17/06 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/38 ,  G06F9/48 ,  G06F17/16 ,  G06F7/24

Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

公开(公告)号：US11294826B2

公开(公告)日：2022-04-05

申请号：US16551587

申请日：2019-08-26

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman ,  Dheera Balasubramanian Samudrala ,  Peter Richard Dent ,  Duc Quang Bui

IPC: G06F9/315 ,  G06F12/0875 ,  G06F11/00 ,  G06F15/76 ,  G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F15/78

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

公开(公告)号：US11106463B2

公开(公告)日：2021-08-31

申请号：US16421920

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Zbiciak ,  Kai Chirca

IPC: G06F9/30

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

公开(公告)号：US10936317B2

公开(公告)日：2021-03-02

申请号：US16422324

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Zbiciak ,  Sahithi Krishna ,  Soujanya Narnur

IPC: G06F12/02 ,  G06F9/30 ,  G06F12/0811

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US10936315B2

公开(公告)日：2021-03-02

申请号：US16237547

申请日：2018-12-31

Applicant: Texas Instruments Incorporated

Inventor： Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/76 ,  G06F9/38 ,  G06F15/78 ,  G06F9/32

Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

公开(公告)号：US20200371799A1

公开(公告)日：2020-11-26

申请号：US16878611

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Soujanya Narnur ,  Timothy David Anderson ,  Mujibur Rahman ,  Duc Quang Bui

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

公开(公告)号：US20200310807A1

公开(公告)日：2020-10-01

申请号：US16846686

申请日：2020-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: In a very long instruction word (VLIW) central processing unit instructions are grouped into execute packets that execute in parallel. A constant may be specified or extended by bits in a constant extension instruction in the same execute packet. If an instruction includes an indication of constant extension, the decoder employs bits of a constant extension instruction to extend the constant of an immediate field. Two or more constant extension slots are permitted in each execute packet, each extending constants for a different predetermined subset of functional unit instructions. In an alternative embodiment, more than one functional unit may have constants extended from the same constant extension instruction employing the same extended bits. A long extended constant may be formed using the extension bits of two constant extension instructions.

公开(公告)号：US20190155605A1

公开(公告)日：2019-05-23

申请号：US16237547

申请日：2018-12-31

Applicant: Texas Instruments Incorporated

Inventor： Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.