公开(公告)号：US20180081734A1

公开(公告)日：2018-03-22

申请号：US15269957

申请日：2016-09-19

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06F9/52 ,  G06F11/07 ,  G06F9/48

CPC classification number: G06F9/5044 ,  G06F9/4881 ,  G06F9/4887 ,  G06F9/52 ,  G06F9/522 ,  G06F11/0757

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

公开(公告)号：US20180081733A1

公开(公告)日：2018-03-22

申请号：US15269952

申请日：2016-09-19

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06F9/48 ,  G06F11/07 ,  G06F9/52

CPC classification number: G06F9/5044 ,  G06F9/4887 ,  G06F9/52 ,  G06F11/0757

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

公开(公告)号：US20170318304A1

公开(公告)日：2017-11-02

申请号：US15653561

申请日：2017-07-19

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Nainala Vyagrheswarudu ,  Vijayavardhan Baireddy ,  Pavan Venkata Shastry

IPC: H04N19/43 ,  H04N19/51

Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.

公开(公告)号：US09538092B2

公开(公告)日：2017-01-03

申请号：US14599201

申请日：2015-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghavi ,  Rajsekhar Allu

IPC: H04N9/73 ,  H04N5/235 ,  H04N5/355 ,  H04N5/345

CPC classification number: H04N5/2355 ,  H04N5/345 ,  H04N5/35581

Abstract: Methods and apparatus to generate wide dynamic range images are disclosed. An example apparatus includes a first processing block having first input, second input to receive input data from an image sensor, and first output; a second processing block having third input, fourth input to receive input data from the image sensor, and second output, at least one of the first and second outputs to output a WDR image based on at least two of the first, second, third and fourth inputs; an architecture recognizer having fifth input and third output, the third output to convey an architecture type of the image sensor; a function selector having fourth output to identify at least one of the first and second processing blocks based on the third output; and a sensor adapter having seventh input coupled to the fourth output and having fifth output coupled to the first and third inputs.

Abstract translation: 公开了产生宽动态范围图像的方法和装置。 示例性装置包括具有第一输入的第一处理块，用于从图像传感器接收输入数据的第二输入和第一输出; 具有第三输入的第二处理块，用于接收来自图像传感器的输入数据的第四输入，以及第二输出，第一和第二输出中的至少一个输出，基于第一，第二，第三和第三输入中的至少两个，输出WDR图像; 第四输入; 具有第五输入和第三输出的架构识别器，用于传送图像传感器的架构类型的第三输出; 功能选择器，具有第四输出，用于基于第三输出来识别第一和第二处理块中的至少一个; 以及传感器适配器，其具有耦合到第四输出的第七输入端，并具有耦合到第一和第三输入端的第五输出端。

公开(公告)号：US20150271512A1

公开(公告)日：2015-09-24

申请号：US14661770

申请日：2015-03-18

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Nainala Vyagrheswarudu ,  Vijayavardhan Baireddy ,  Pavan Venkata Shastry

IPC: H04N19/46 ,  H04N19/51

CPC classification number: H04N19/43 ,  H04N19/51

Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.

Abstract translation: 公开了支持动态帧填充的视频硬件引擎。 视频硬件引擎包括外部存储器。 外部存储器存储参考帧。 参考帧包括多个参考像素。 运动估计（ME）引擎接收当前LCU（最大编码单元），并且定义当前LCU周围的运动估计周围的搜索区域。 ME引擎接收与当前LCU对应的一组参考像素。 从外部存储器接收多个参考像素的参考像素集合。 当搜索区域的一部分区域在参考帧之外时，ME引擎沿着参考帧的边缘焊接一组重复像素。

公开(公告)号：US20150271494A1

公开(公告)日：2015-09-24

申请号：US14661711

申请日：2015-03-18

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Pavan Venkata Shastry

IPC: H04N19/115 ,  G06F13/28 ,  H04N19/423

CPC classification number: H04N19/115 ,  G06F13/28 ,  H04N19/423

Abstract: A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N.

Abstract translation: 公开了一种低功率视频硬件引擎。 视频硬件引擎包括视频硬件加速器单元。 共享存储器耦合到视频硬件加速器单元，并且加扰器耦合到共享存储器。 vDMA（视频直接存储器访问）引擎耦合到加扰器，并且外部存储器耦合到vDMA引擎。 加扰器从vDMA引擎接收LCU（最大编码单元）。 LCU包括N×N个像素，扰频器对LCU中的N×N个像素进行加扰，以产生具有M×M个像素的多个块。 N和M是整数，M小于N.

公开(公告)号：US20150207974A1

公开(公告)日：2015-07-23

申请号：US14599201

申请日：2015-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghavi ,  Rajsekhar Allu

IPC: H04N5/235 ,  H04N5/374 ,  H04N5/3725 ,  H04N5/355 ,  H04N5/357

CPC classification number: H04N5/2355 ,  H04N5/345 ,  H04N5/35581

Abstract: Methods and apparatus to generate wide dynamic range images are disclosed. An example apparatus includes a first processing block having first input, second input to receive input data from an image sensor, and first output; a second processing block having third input, fourth input to receive input data from the image sensor, and second output, at least one of the first and second outputs to output a WDR image based on at least two of the first, second, third and fourth inputs; an architecture recognizer having fifth input and third output, the third output to convey an architecture type of the image sensor; a function selector having fourth output to identify at least one of the first and second processing blocks based on the third output; and a sensor adapter having seventh input coupled to the fourth output and having fifth output coupled to the first and third inputs.

Abstract translation: 公开了产生宽动态范围图像的方法和装置。 示例性装置包括具有第一输入的第一处理块，用于从图像传感器接收输入数据的第二输入和第一输出; 具有第三输入的第二处理块，用于接收来自图像传感器的输入数据的第四输入，以及第二输出，第一和第二输出中的至少一个输出，基于第一，第二，第三和第三输入中的至少两个，输出WDR图像; 第四输入; 具有第五输入和第三输出的架构识别器，用于传送图像传感器的架构类型的第三输出; 功能选择器，具有第四输出，用于基于第三输出来识别第一和第二处理块中的至少一个; 以及传感器适配器，其具有耦合到第四输出的第七输入端，并具有耦合到第一和第三输入端的第五输出端。

公开(公告)号：US12236562B2

公开(公告)日：2025-02-25

申请号：US18465250

申请日：2023-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gang Hua ,  Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody

IPC: G06T5/80 ,  G06T3/18 ,  G06T7/60 ,  G06T11/40

Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.

公开(公告)号：US12185007B2

公开(公告)日：2024-12-31

申请号：US18091798

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Mihir Narendra Mody ,  Rajasekhar Allu

IPC: H04N25/77 ,  H04N23/698 ,  H04N23/81

Abstract: In an example, a method includes receiving image data of an input image having lines therein. The method also includes storing a first portion of the image data in a circular buffer in a first memory, wherein the first portion begins at a circular buffer start line in the input image and ends at a circular buffer end line in the input image. The method includes storing a second portion of the image data in a linear buffer in a second memory, where the second portion is non-overlapping with the first portion. The method includes processing the second portion of the image data to produce a first block of an output image. The method includes processing the first portion of the image data to produce a second block of the output image.

公开(公告)号：US12050929B2

公开(公告)日：2024-07-30

申请号：US17123653

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.