公开(公告)号：US11211360B2

公开(公告)日：2021-12-28

申请号：US16745345

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

Abstract: A passive device module includes a first tier, a second tier and connective terminals. The first tier includes a first semiconductor chip and a first encapsulant. The first semiconductor chip has contact posts. The encapsulant encapsulates the first semiconductor chip. The second tier is disposed on the first tier, and includes a second semiconductor chip, through interlayer walls, and a second encapsulant. The through interlayer walls are locate beside and face sidewalls of the second semiconductor chip and are electrically connected to the contact posts. The second encapsulant encapsulates the second semiconductor chip and the through interlayer walls. The connective terminals are disposed over the second tier and are electrically connected to the first semiconductor chip via the through interlayer walls. The first and second semiconductor chips include passive devices.

公开(公告)号：US11195817B2

公开(公告)日：2021-12-07

申请号：US16666388

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Chih-Yuan Chang

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L23/40

Abstract: A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat sink is fastened to the reconstructed wafer.

公开(公告)号：US20210305226A1

公开(公告)日：2021-09-30

申请号：US16830282

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Wei-Ting Chen

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L23/29 ,  H01L23/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538 ,  H01L21/683 ,  H01L25/065

Abstract: Embodiments of the disclosure provide a package structure and method of forming the same. The package structure includes a first die, a first encapsulant, a first RDL structure, a die stack structure and a second encapsulant. The first encapsulant laterally encapsulates the first die. The first RDL structure is electrically connected to the first die, and disposed on a first side of the first die and the first encapsulant. The die stack structure is electrically connected to the first die and disposed on a second side of the first die opposite to the first side. The second encapsulant is located over the first encapsulant and laterally encapsulating the die stack structure. A sidewall of the first encapsulant is aligned with a sidewall of the second encapsulant.

公开(公告)号：US11094634B2

公开(公告)日：2021-08-17

申请号：US16231622

申请日：2018-12-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Yuan Chang ,  Jiun-Yi Wu ,  Jeng-Shien Hsieh ,  Tin-Hao Kuo

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L21/683

Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures. The circuit layer is disposed over a surface of the flexible core, and electrically connected with the interconnection structures.

公开(公告)号：US11062998B2

公开(公告)日：2021-07-13

申请号：US16547567

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Wei-Ting Chen ,  Chien-Hsun Chen ,  Shih-Ya Huang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

Abstract: A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies.

公开(公告)号：US20210202453A1

公开(公告)日：2021-07-01

申请号：US17181279

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chieh Chang ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Hsing-Kuo Hsia ,  Chen-Hua Yu

IPC: H01L25/16 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522

Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.

公开(公告)号：US20210125960A1

公开(公告)日：2021-04-29

申请号：US16666388

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Chih-Yuan Chang

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/40 ,  H01L23/31 ,  H01L25/00

Abstract: A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat sink is fastened to the reconstructed wafer.

公开(公告)号：US10962711B2

公开(公告)日：2021-03-30

申请号：US16569673

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chieh Chang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: G02B6/12 ,  G02B6/13

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes a substrate and a dielectric layer. The substrate has a wave guide pattern. The dielectric layer is disposed over the substrate. The photonic die is encapsulated by the encapsulant. The wave guide structure spans over the front side of the photonic die and a top surface of the encapsulant, and penetrates the dielectric layer to be optically coupled with the wave guide pattern.

公开(公告)号：US20200335477A1

公开(公告)日：2020-10-22

申请号：US16923115

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US20200321288A1

公开(公告)日：2020-10-08

申请号：US16908284

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chen-Hua Yu ,  Chih-Yuan Chang

IPC: H01L23/552 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L23/50 ,  H01L21/683

Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.