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    3D RAM SL/BL contact modulation
    81.
    发明授权
    3D RAM SL/BL contact modulation 有权

    公开(公告)号：US11569264B2

    公开(公告)日：2023-01-31

    申请号：US17122228

    申请日：2020-12-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chen Wang ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11556

    Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

    Three-Dimensional Memory Device with Ferroelectric Material
    85.
    发明申请
    Three-Dimensional Memory Device with Ferroelectric Material 有权

    公开(公告)号：US20220359542A1

    公开(公告)日：2022-11-10

    申请号：US17814648

    申请日：2022-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

    IPC: H01L27/1159 ,  H01L27/11597 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/24

    Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

    3D semiconductor package including memory array
    86.
    发明授权
    3D semiconductor package including memory array 有权

    公开(公告)号：US11444069B2

    公开(公告)日：2022-09-13

    申请号：US17138270

    申请日：2020-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Yu-Ming Lin

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L27/1159 ,  H01L27/11597 ,  H01L23/48 ,  H01L29/24

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

    Memory cell and method
    89.
    发明授权
    Memory cell and method 有权

    公开(公告)号：US11342334B2

    公开(公告)日：2022-05-24

    申请号：US16901885

    申请日：2020-06-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

    IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423

    Abstract: An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

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