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    Memory device and method of forming the same
    1.
    发明授权
    Memory device and method of forming the same 有权

    公开(公告)号：US11502128B2

    公开(公告)日：2022-11-15

    申请号：US17123925

    申请日：2020-12-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin

    IPC: H01L27/24 ,  H01L45/00 ,  H01L29/78 ,  H01L23/522 ,  G11C7/18 ,  G11C8/14

    Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

    Semiconductor structure having memory device and method of forming the same
    2.
    发明授权
    Semiconductor structure having memory device and method of forming the same 有权

    公开(公告)号：US11411011B2

    公开(公告)日：2022-08-09

    申请号：US17132305

    申请日：2020-12-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

    IPC: H01L27/11502 ,  H01L27/11585 ,  G11C11/22 ,  G11C5/06

    Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.

    THREE-DIMENSIONAL MEMORY DEVICE WITH FERROELECTRIC MATERIAL
    3.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH FERROELECTRIC MATERIAL 有权

    公开(公告)号：US20210375928A1

    公开(公告)日：2021-12-02

    申请号：US17033006

    申请日：2020-09-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

    IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/24 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

    Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

    Three-dimensional memory device with ferroelectric material
    4.
    发明授权
    Three-dimensional memory device with ferroelectric material 有权

    公开(公告)号：US11616080B2

    公开(公告)日：2023-03-28

    申请号：US17033006

    申请日：2020-09-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

    IPC: H01L27/1159 ,  H01L27/11597 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/24

    Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

    Memory cell with temperature modulated read voltage
    5.
    发明授权
    Memory cell with temperature modulated read voltage 有权

    公开(公告)号：US11532357B2

    公开(公告)日：2022-12-20

    申请号：US17149985

    申请日：2021-01-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Win-San Khwa

    IPC: G11C11/00 ,  G11C13/00

    Abstract: An integrated chip has an array of memory cells disposed over a semiconductor substrate and a driver circuit. The driver circuit provides the array with a read voltage that varies in relation to an approximate temperature of the memory array to ameliorate temperature dependencies in read currents. The driver circuit may vary the read voltage in an inverse relationship with temperature. The read voltage may be varied continuous or stepwise and the driver circuit may use a table lookup. Optionally, the driver circuit measures a current and modulates the read voltage until the current is within a target range. The memory cells may be multi-level phase change memory cells that include a plurality phase change element disposed between a bottom electrode and a top electrode. Modulating the read voltage to reduce temperature-dependent current variations is particularly useful for multi-level cells.

    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210399048A1

    公开(公告)日：2021-12-23

    申请号：US17108243

    申请日：2020-12-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210399014A1

    公开(公告)日：2021-12-23

    申请号：US17137768

    申请日：2020-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

    IPC: H01L27/11597 ,  H01L27/11587

    Abstract: A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.

    MEMORY DEVICES AND METHODS OF FORMING THE SAME
    8.
    发明申请
    MEMORY DEVICES AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210249597A1

    公开(公告)日：2021-08-12

    申请号：US16785673

    申请日：2020-02-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

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