公开(公告)号：US09496276B2

公开(公告)日：2016-11-15

申请号：US14092912

申请日：2013-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11573

Abstract: A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the substrate. The split gate memory device is located on the substrate and comprises a memory gate and a select gate. The memory gate and the select gate are adjacent to and electrically isolated with each other. A top of the select gate is higher than a top of the memory gate.

Abstract translation: 半导体器件包括衬底，至少一个逻辑器件和分离栅极存储器件。 至少一个逻辑器件位于衬底上。 分离栅极存储器件位于衬底上并且包括存储器栅极和选择栅极。 存储器栅极和选择栅极彼此相邻并且电隔离。 选择栅极的顶部高于存储器栅极的顶部。

公开(公告)号：US09171849B2

公开(公告)日：2015-10-27

申请号：US14032222

申请日：2013-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Min Chan ,  Wei-Cheng Wu ,  Yen-Huei Chen

IPC: G11C5/06 ,  H01L27/11 ,  G11C11/412 ,  G11C11/413 ,  G11C8/16 ,  H01L27/06 ,  G11C5/02 ,  G11C8/08

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C8/08 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0688 ,  H01L27/1104 ,  H01L2224/48227 ,  H01L2224/73265

Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

Abstract translation: 三维双端口位单元通常包括设置在第一层上的第一部分，其中第一部分包括多个端口元件。 双端口位单元还包括设置在使用至少一个通孔相对于第一层垂直堆叠的第二层上的第二部分，其中第二部分包括闩锁。

公开(公告)号：US20140133219A1

公开(公告)日：2014-05-15

申请号：US13674192

申请日：2012-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C5/14 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.

Abstract translation: 本公开的一些实施例涉及具有单元电压发生器的存储器阵列，其被配置为向多个存储器单元提供单元电压报头。 电池电压发生器通过电源电压线连接到存储器单元，并控制存储器单元的电源电压。 电池电压发生器具有耦合在电源电压线的控制节点和接地端子之间的下拉元件以及在控制节点和电池电压源之间并联连接的一个或多个上拉元件。 控制单元被配置为向上拉元件的输入节点提供一个或多个可变值上拉使能信号。 可变值上拉使能信号操作上拉元件以选择性地将电源电压线与电池电压源连接，以提供具有高压摆率的电池电压头。