公开(公告)号：US20130313572A1

公开(公告)日：2013-11-28

申请号：US13953349

申请日：2013-07-29

申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC分类号： H01L29/78 ,  H01L29/16

CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.

公开(公告)号：US20130175545A1

公开(公告)日：2013-07-11

申请号：US13345457

申请日：2012-01-06

申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC分类号： H01L29/161 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.

摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。

公开(公告)号：US20130052783A1

公开(公告)日：2013-02-28

申请号：US13216921

申请日：2011-08-24

申请人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Jan Hoentschel

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26513 ,  H01L21/26526 ,  H01L29/7848

摘要： Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.

摘要翻译： 这里公开了在NMOS晶体管器件中形成应力硅 - 碳区域的各种方法。 在一个实例中，本文公开的方法包括在包括多个N掺杂区域的半导体衬底的表面上方形成无定形碳层，并对无定形碳层进行离子注入工艺以将碳原子从层 并且将移动的碳原子驱动到衬底中的N掺杂区域中。

公开(公告)号：US20120153399A1

公开(公告)日：2012-06-21

申请号：US13192620

申请日：2011-07-28

申请人： Jan Hoentschel ,  Stefan Flachowsky ,  Steven Langdon ,  Thilo Scheiper

发明人： Jan Hoentschel ,  Stefan Flachowsky ,  Steven Langdon ,  Thilo Scheiper

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.

摘要翻译： 漏极和源极区域可以至少部分地由原位掺杂的外延生长的半导体材料形成，用于为低功率和高性能应用设计的复杂半导体器件中的互补晶体管。 为此，空穴可以用原位掺杂的半导体材料重新填充，在一些说明性实施例中，还可以在互补晶体管的沟道区域中提供期望的应变。

公开(公告)号：US08916433B2

公开(公告)日：2014-12-23

申请号：US13406869

申请日：2012-02-28

申请人： Thilo Scheiper ,  Peter Baars ,  Sven Beyer

发明人： Thilo Scheiper ,  Peter Baars ,  Sven Beyer

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/76 ,  H01L21/461 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/10 ,  H01L21/762

CPC分类号： H01L21/823878 ,  H01L21/28123 ,  H01L21/76232 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7848

摘要： When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.

摘要翻译： 当在早期制造阶段形成高k金属栅电极结构时，可以通过减小隔离区的表面形貌来改善封装的完整性，从而改善敏感栅极材料的完整性。 为此，与传统的二氧化硅材料组合提供了具有优良蚀刻电阻率的电介质盖层。

公开(公告)号：US20120261765A1

公开(公告)日：2012-10-18

申请号：US13533807

申请日：2012-06-26

申请人： Sven Beyer ,  Klaus Hempel ,  Thilo Scheiper ,  Stefanie Steiner

发明人： Sven Beyer ,  Klaus Hempel ,  Thilo Scheiper ,  Stefanie Steiner

IPC分类号： H01L21/28 ,  H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545

摘要： In a replacement gate approach in sophisticated semiconductor devices, the placeholder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack.

摘要翻译： 在复杂半导体器件中的替代栅极方法中，分别去除不同类型的栅电极结构的占位符材料。 此外，可以在所得到的栅极开口中选择性地形成电极金属，从而在调整不同类型的栅电极结构的各自的功函数方面提供优异的工艺条件。 在一个说明性实施例中，在不同类型的栅极电极结构中单独形成栅极开口可以基于设置在栅极层叠层中的掩模材料。

公开(公告)号：US08652956B2

公开(公告)日：2014-02-18

申请号：US13533807

申请日：2012-06-26

申请人： Sven Beyer ,  Klaus Hempel ,  Thilo Scheiper ,  Stefanie Steiner

发明人： Sven Beyer ,  Klaus Hempel ,  Thilo Scheiper ,  Stefanie Steiner

IPC分类号： H01L21/28 ,  H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545

摘要： In a replacement gate approach in sophisticated semiconductor devices, the placeholder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack.

摘要翻译： 在复杂半导体器件中的替代栅极方法中，分别去除不同类型的栅电极结构的占位符材料。 此外，可以在所得到的栅极开口中选择性地形成电极金属，从而在调整不同类型的栅电极结构的各自的功函数方面提供优异的工艺条件。 在一个说明性实施例中，在不同类型的栅极电极结构中单独形成栅极开口可以基于设置在栅极层叠层中的掩模材料。

公开(公告)号：US08232188B2

公开(公告)日：2012-07-31

申请号：US12905440

申请日：2010-10-15

申请人： Sven Beyer ,  Klaus Hempel ,  Thilo Scheiper ,  Stefanie Steiner

发明人： Sven Beyer ,  Klaus Hempel ,  Thilo Scheiper ,  Stefanie Steiner

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545

摘要： In a replacement gate approach in sophisticated semiconductor devices, the place-holder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack.

摘要翻译： 在复杂半导体器件中的替代栅极方法中，分别去除不同类型的栅电极结构的放置保持材料。 此外，可以在所得到的栅极开口中选择性地形成电极金属，从而在调整不同类型的栅电极结构的各自的功函数方面提供优异的工艺条件。 在一个说明性实施例中，在不同类型的栅极电极结构中单独形成栅极开口可以基于设置在栅极层叠层中的掩模材料。

公开(公告)号：US20110156153A1

公开(公告)日：2011-06-30

申请号：US12905711

申请日：2010-10-15

申请人： Sven Beyer ,  Jande Hoentschel ,  Uwe Griebenow ,  Thilo Scheiper

发明人： Sven Beyer ,  Jande Hoentschel ,  Uwe Griebenow ,  Thilo Scheiper

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/7848

摘要： In a process strategy for forming high-k metal gate electrode structures in an early manufacturing phase, a predoped semiconductor material may be used in order to reduce the Schottky barrier between the semiconductor material and the conductive cap material of the gate electrode structures. Due to the substantially uniform material characteristics of the predoped semiconductor material, any patterning-related non-uniformities during the complex patterning process of the gate electrode structures may be reduced. The predoped semiconductor material may be used for gate electrode structures of complementary transistors.

摘要翻译： 在用于在早期制造阶段形成高k金属栅电极结构的工艺策略中，可以使用预制半导体材料，以便减少半导体材料与栅电极结构的导电盖材料之间的肖特基势垒。 由于预制半导体材料的材料特性基本上均匀，可能会降低栅电极结构复杂构图工艺过程中任何与图案相关的不均匀性。 预制半导体材料可用于互补晶体管的栅电极结构。

公开(公告)号：US08349695B2

公开(公告)日：2013-01-08

申请号：US12848741

申请日：2010-08-02

申请人： Thilo Scheiper ,  Andy Wei ,  Martin Trentzsch

发明人： Thilo Scheiper ,  Andy Wei ,  Martin Trentzsch

IPC分类号： H01L23/336

CPC分类号： H01L21/823462 ,  H01L21/823857

摘要： In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided.

摘要翻译： 在复杂的制造技术中，工作功能和晶体管元件的阈值电压可以在早期制造阶段通过提供在高k电介质材料内调节物质的功函数来调节，其中栅极电介质材料具有基本上相同的空间分布 不同厚度。 在结合工作功能调整物质之后，可以通过选择性地形成额外的介电层来调节栅极电介质材料的最终厚度，使得栅电极结构的进一步图案化可以以与常规制造高度的相容性来实现 技术 因此，可以避免用于重新调整具有不同厚度栅极电介质材料的晶体管的阈值电压的非常复杂的工艺。