公开(公告)号：US08580659B2

公开(公告)日：2013-11-12

申请号：US13262656

申请日：2011-07-25

申请人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

发明人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

IPC分类号： H01L21/20

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation.

摘要翻译： 本发明公开了一种制造基于SOI衬底的高迁移率双通道材料的方法，其中压缩应变SiGe在常规SOI衬底上外延生长以用作PMOSFET的沟道材料; Si在SiGe上表面生长，采用离子注入和退火等方法，使部分应变SiGe弛豫并向其上的Si层转移应变，形成作为NMOSFET的沟道材料的应变Si材料。 通过简单的工艺和易于实现，该方法可以同时为NMOSFET和PMOSFET提供高迁移率沟道材料，可以很好地满足NMOSFET和PMOSFET器件同时提高性能的要求，从而为CMOS工艺提供潜在的沟道材料 下一代。

公开(公告)号：US20130273714A1

公开(公告)日：2013-10-17

申请号：US13976486

申请日：2010-12-31

申请人： Xing Wei ,  Zhongdang Wang ,  Fei Ye ,  Gongbai Cao ,  Chenglu Lin ,  Miao Zhang ,  Xi Wang

发明人： Xing Wei ,  Zhongdang Wang ,  Fei Ye ,  Gongbai Cao ,  Chenglu Lin ,  Miao Zhang ,  Xi Wang

IPC分类号： H01L21/02

CPC分类号： H01L21/3226 ,  H01L21/76254

摘要： A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.

摘要翻译： 通过沟槽工艺制备具有掩埋绝缘层的半导体衬底的方法包括以下步骤：提供器件衬底和支撑衬底; 在所述器件基板的表面上形成绝缘层; 在所述器件基板上进行加热处理，以在所述器件基板的表面上形成剥离区域; 将具有绝缘层的器件基板与支撑基板接合，使得绝缘层夹在器件基板和支撑基板之间; 退火和加强粘合界面，使得接合界面的粘附水平满足以下倒角研磨，减薄和抛光工艺中的要求; 在接合的器件基板上进行倒角研磨，变薄和抛光工艺。

公开(公告)号：US08450195B2

公开(公告)日：2013-05-28

申请号：US12937258

申请日：2010-07-14

申请人： Jing Chen ,  Xiaolu Huang ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

发明人： Jing Chen ,  Xiaolu Huang ,  Jiexin Luo ,  Qingqing Wu ,  Xi Wang

IPC分类号： H01L21/425

CPC分类号： H01L21/26586 ,  H01L29/66545 ,  H01L29/78615

摘要： The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process.

摘要翻译： 本发明公开了一种通过大的倾斜离子注入降低SOI MOS器件的浮体效应的方法，包括以下步骤：（a）将倾斜方向的离子注入到具有形成高掺杂P区的掩埋绝缘层的NMOS中 NMOS的源极区域和掩埋绝缘层之上，其中NMOS的纵向线与倾斜方向之间的角度为15至45度。 通过这种方法，源区下的高掺杂P区和高掺杂N区形成隧道结，以减少浮体效应。 此外，芯片面积不会增加，制造工艺简单，方法与常规CMOS工艺兼容。

公开(公告)号：US08437273B2

公开(公告)日：2013-05-07

申请号：US12488921

申请日：2009-06-22

申请人： Xi Wang ,  Paparao Palacharla ,  Takao Naito

发明人： Xi Wang ,  Paparao Palacharla ,  Takao Naito

IPC分类号： H04L12/28 ,  G08C15/00 ,  G06F15/173

CPC分类号： H04J3/1682 ,  H04J3/085 ,  H04Q11/0062 ,  H04Q2011/0086

摘要： According to one embodiment, allocating demand includes receiving a demand graph that describes demands of a network. One or more weights are calculated for each demand. The demands are allocated according to the weights of the demands to optimize optical line card sharing.

摘要翻译： 根据一个实施例，分配需求包括接收描述网络需求的需求图。 为每个需求计算一个或多个权重。 根据需求权重分配要求，优化光线路卡共享。

公开(公告)号：US08422288B2

公开(公告)日：2013-04-16

申请号：US12937257

申请日：2010-07-14

申请人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

发明人： Deyuan Xiao ,  Xiaolu Huang ,  Jing Chen ,  Xi Wang

IPC分类号： G11C11/34

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802

摘要： The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process.

摘要翻译： 本发明公开了一种利用浮体效应的DRAM单元及其制造方法。 DRAM单元包括设置在掩埋氧化物层上的P型半导体区域，设置在P型半导体区域上的N型半导体区域，设置在N型半导体区域上的栅极区域和围绕P型半导体的电隔离区域 区域和N型半导体区域。 将浮体效应的二极管作为存储节点。 通过带之间的隧道效应，电子聚集在浮体中，其被定义为第一存储状态; 通过PN结的正向偏压，电子从浮体发出，或者将空穴注入到浮动体中，其被定义为第二存储状态。 本发明提供一种利用高密度的浮体效应的高效率DRAM单元，其具有低功耗，制造工艺简单，并且与常规CMOS和常规逻辑电路制造工艺兼容。

公开(公告)号：US20130089317A1

公开(公告)日：2013-04-11

申请号：US13348915

申请日：2012-01-12

申请人： Qiong Zhang ,  Xi Wang ,  Paparao Palacharla ,  Motoyoshi Sekiya

发明人： Qiong Zhang ,  Xi Wang ,  Paparao Palacharla ,  Motoyoshi Sekiya

IPC分类号： H04B10/00 ,  H04J14/00

CPC分类号： H04Q11/0062 ,  H04J14/0284 ,  H04J14/0295 ,  H04L41/0654 ,  H04Q2011/0081

摘要： In accordance with embodiments of the present disclosure, a method may include sorting potential optical layer link failures in a network in an increasing order of failed traffic amount. The method may further include, for each potential optical link failure in increasing order of failed traffic amount: determining the additional higher layer link capacity required on existing higher layer links associated with the potential optical link failure using higher layer restoration of the potential optical link failure; determining the additional optical layer capacity required for restoring the existing higher layer links associated with the potential optical link failure using optical layer restoration; and selecting one of the higher layer and the optical layer as a restoration layer for restoration of the existing higher layer links associated with the potential optical link failure based on the determined additional higher layer link capacity and the determined additional optical layer capacity.

摘要翻译： 根据本公开的实施例，一种方法可以包括按照故障业务量的增加顺序对网络中的潜在光层链路故障进行排序。 该方法还可以包括：针对每个潜在的光链路故障以增加的故障业务量的顺序：使用更高层恢复潜在光链路故障来确定与潜在光链路故障相关联的现有较高层链路上所需的附加较高层链路容量 ; 使用光学层恢复来确定恢复与潜在光链路故障相关联的现有较高层链路所需的附加光层容量; 并且基于所确定的附加较高层链路容量和所确定的附加光层容量，选择较高层和光层之一作为恢复层，用于恢复与潜在光链路故障相关联的现有较高层链路。

公开(公告)号：US08354714B2

公开(公告)日：2013-01-15

申请号：US13132879

申请日：2010-09-07

申请人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Jiexin Luo ,  Qingqing Wu ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L29/78615 ,  H01L29/458 ,  H01L29/78621

摘要： The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology.

摘要翻译： 本发明公开了一种具有BTS结构的SOI MOS器件及其制造方法。 SOI MOS器件的源极区域包括：两个重掺杂N型区域，形成在两个重掺杂N型区域之间的重掺杂P型区域，在重掺杂N型区域上形成的硅化物， 掺杂P型区域和与硅化物接触的浅N型区域; 在重掺杂的P型区域和其上的硅化物之间形成欧姆接触以释放积聚在SOI MOS器件的体区中的空穴，并且消除其浮体效应而不增加芯片面积，并且还克服了诸如降低有效性 现有技术的BTS结构中的设备的信道宽度。 该制造方法包括以下步骤：通过离子注入形成重掺杂的P型区，在源区上方形成金属层，并通过金属层与Si之间的Si之间的热处理形成硅化物。 本发明中的器件可以通过简化的制造工艺制造，与传统CMOS技术具有很好的兼容性。

公开(公告)号：US08354310B2

公开(公告)日：2013-01-15

申请号：US13131126

申请日：2010-09-07

申请人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Xiaolu Huang ,  Xi Wang

发明人： Jing Chen ,  Qingqing Wu ,  Jiexin Luo ,  Xiaolu Huang ,  Xi Wang

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/331

CPC分类号： H01L29/458 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78621

摘要： The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology.

摘要翻译： 本发明公开了一种具有源/体欧姆接触的SOI MOS器件的制造方法。 该制造方法包括以下步骤：首先产生栅极区域，然后进行高剂量源和漏极掺杂以形成轻掺杂的N型源极区域和轻掺杂的N型漏极区域; 形成围绕所述栅极区域的绝缘间隔物; 通过在N型Si源极区域的位置处具有开口的掩模在倾斜方向上进行大倾斜重掺杂P离子注入，并且将P离子注入到N型Si源极区域和N型漏极区域之间的空间中，以 形成重掺杂P型区; 最后在N型Si源区上形成金属层，然后通过热处理使金属层与下面残留的Si材料之间的反应形成硅化物。 在通过本发明的方法制备的器件中，在硅化物和附近的重掺杂P型区域之间形成欧姆接触，以释放积累在SOI MOS器件的体区中的空穴并消除浮体效应 其中。 此外，本发明的器件还具有以下优点，例如有限的芯片面积，简化的制造工艺和与传统CMOS技术的很好的兼容性。

公开(公告)号：US08330228B2

公开(公告)日：2012-12-11

申请号：US12810694

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/092

CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/42392

摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.

摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有圆形截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下，电流流过整个圆柱形通道，以实现高载流子迁移率，降低低频噪声，防止多晶硅栅极耗尽和短沟道效应，并增加器件的阈值电压。

公开(公告)号：US20120129320A1

公开(公告)日：2012-05-24

申请号：US13260757

申请日：2011-07-25

申请人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

发明人： Miao Zhang ,  Bo Zhang ,  Zhongying Xue ,  Xi Wang

IPC分类号： H01L21/20

CPC分类号： C30B29/52 ,  C30B1/00 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/456

摘要： The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance.

摘要翻译： 本发明公开了一种通过引入Al中间层的NiSiGe外延生长方法，包括在SiGe层的表面上沉积Al薄膜，随后在Al薄膜上沉积Ni层，然后在Ni之间进行退火处理 SiGe层的SiGe材料，形成NiSiGe材料。 由于Al中间层的阻挡效应，NiSiGe层具有单晶结构，与SiGe衬底的平坦界面，厚度可达0.3nm，显着提高了界面性能。