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公开(公告)号：US4758963A
公开(公告)日：1988-07-19
申请号：US52126
申请日：1987-05-15
CPC分类号： G01R13/20
摘要： An oscilloscope to sequentially store, process and display an electrical input signal according to various signal events and characteristics. The oscilloscope is physically and functionally modular having both selectable hardware configurations from among various "plug-in" modules and selectable processing and display features chosen from among a predetermined selection by software control contained, in part, within the plug-in modules. The particular control settings, as well as a representation of the signal itself, is recorded on a removable storage device, such as a magnetic disc. High frequency signals are sampled, digitized and stored in a high speed intercascaded signal memory, independent from the program and data memory associated with the oscilloscope signal processing.
摘要翻译： 示波器根据各种信号事件和特性依次存储，处理和显示电输入信号。 示波器在物理上和功能上是模块化的，其具有来自各种“插件”模块的可选择的硬件配置以及通过部分地包含在插件模块内的软件控制从预定选择中选择的可选处理和显示特征。 特定控制设置以及信号本身的表示被记录在诸如磁盘的可移动存储设备上。 高频信号采样，数字化并存储在高速级联信号存储器中，独立于与示波器信号处理相关的程序和数据存储器。
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82.发明授权
公开(公告)号：US4654584A
公开(公告)日：1987-03-31
申请号：US808454
申请日：1985-12-12
申请人： Colin Gyles
发明人： Colin Gyles
CPC分类号： G01R13/345 , H03M1/1285 , H03M1/46
摘要： A circuit for precisely measuring very high-speed recurring waveforms includes a comparator coupled between an analog input terminal and a successive approximation register. A digital-to-analog converter is also coupled between the digital output circuit of the successive approximation register and the second input terminal of the comparator, and a high-speed digital latch is coupled between the output of the comparator and the input of the successive approximation register for freezing the output states of the comparator upon the application of hold signals from a hold signal generator means, so that a first sequential series of hold signals are applied to the latch, coincident in time with the occurrence of a first portion of the recurring analog waveforms being measured, until the successive approximation register completes its measurement of the voltage amplitude of such first portion. A counter in the hold signal generator means is thereafter stepped, to enable the measurement of a second portion of the recurring waveform, adjacent the first portion, to be carried out by the application of a second series of hold signals, each coincident in time with the occurrence of the second portion of the waveform, until the voltage amplitude at the second portion is evaluated by the iterative operation of the successive approximation register. The counter is again stepped, and the process is repeated until numerous points upon the recurring waveform under examination are measured.
摘要翻译： 用于精确测量非常高速循环波形的电路包括耦合在模拟输入端和逐次逼近寄存器之间的比较器。 数模转换器还耦合在逐次逼近寄存器的数字输出电路和比较器的第二输入端之间，高速数字锁存器耦合在比较器的输出端和连续的输入端之间 近似寄存器，用于在从保持信号发生器装置施加保持信号时冻结比较器的输出状态，使得第一顺序一系列保持信号施加到锁存器，与时间上的第一部分的出现一致 重复的模拟波形被测量，直到逐次逼近寄存器完成其对这样的第一部分的电压幅度的测量。 保持信号发生器装置中的计数器此后是步进的，以便能够通过应用第二系列保持信号来执行与第一部分相邻的重复波形的第二部分的测量，每个保持信号的时间与 直到第二部分的电压振幅通过逐次逼近寄存器的迭代操作来评估波形的第二部分的出现。 计数器再次步进，重复该过程，直到测量出复发波形的多个点为止。
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83.发明授权
公开(公告)号：US4607248A
公开(公告)日：1986-08-19
申请号：US516765
申请日：1983-07-25
申请人： Alexander T. Botka , Evan Colton
发明人： Alexander T. Botka , Evan Colton
CPC分类号： H03M1/74
摘要： A D/A converter for converting a digital signal having a number of bits to an analog signal. The converter is fabricated in an integrated circuit digital array including a register for storing the particular number of bits, a buffer circuit for receiving those bits from the register, and an analog current switching network. The analog current switching network includes a number of current switching circuits, each of which provides the proper current output in response to the delivery of an associated bit from the buffer circuit. Each current switching circuit includes an emitter coupled switch circuit having two pluralities of parallel connected transistor cells with the bases of one of the plurality of transistor cells connected with the buffer circuit and the bases of the other of the plurality of transistor cells connected with the current switching circuit. The current switching circuit includes a first transistor cell with its emitter connected to the base of the other of the plurality of transistor cells in the emitter coupled switch circuit. A voltage summing network responsive to the current output from the analog current switching network provides voltages representative of the bit presented by the associated buffer circuit.
摘要翻译： 一种用于将具有多个位的数字信号转换为模拟信号的D / A转换器。 该转换器采用集成电路数字阵列制造，该集成电路数字阵列包括用于存储特定位数的寄存器，用于从寄存器接收这些位的缓冲电路和模拟电流交换网络。 模拟电流开关网络包括多个电流开关电路，每个电流开关电路响应于来自缓冲电路的相关位的传送而提供适当的电流输出。 每个电流开关电路包括具有两个并联的晶体管单元的发射极耦合开关电路，其中多个晶体管单元之一的基极与缓冲电路连接，并且多个晶体管单元中的另一个晶体管单元的基极与电流连接 开关电路。 电流开关电路包括第一晶体管单元，其发射极连接到发射极耦合开关电路中的多个晶体管单元中的另一个的基极。 响应于来自模拟电流开关网络的电流输出的电压求和网络提供代表相关联的缓冲电路所呈现的位的电压。
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84.发明授权Full floating point vector processor with dynamically configurable multifunction pipelined ALU 失效具有可动态配置的多功能流水线ALU的全浮点矢量处理器
公开(公告)号：US4589067A
公开(公告)日：1986-05-13
申请号：US498877
申请日：1983-05-27
CPC分类号： G06F9/3887 , G06F9/226 , G06F9/30036 , G06F9/3879
摘要： A full floating point vector processor includes a master processing unit having DMA I/O means, a wide bandwidth data memory having static RAM and/or interleaved dynamic RAM, an address generator operative to provide address generation for data loaded in the data memory, a concurrently operating pipeline control sequencer operative to provide fully programmable horizontal format microinstructions synchronously with the addresses generated by the address generator, and a pipelined arithmetic and logical unit responsive to the addressed data and to the synchronously provided microinstructions and operative to evaluate one of a user selectable plurality of computationally intensive functions. The address generator, the pipeline controlsequencer, and the master processing unit are configured in parallel. The address generator includes means operative to provide pipeline input and output data dependent address generation. The microinstruction controlled pipelined arithmetic and logical unit includes two register files controllably interconnectable over feedforward and feedback data flow paths, a user selectable fixed or floating point format multiplier, a user selectable fixed or floating point format arithmetic and logical unit, and a sign latch coupled between the arithmetic and logical unit and one of the register files. The sign latch microinstruction control is operative to provide the arithmetic and logical unit with a data dependent decison making capability. A microinstruction controlled write address FIFO and a read address FIFO are coupled to the data memory.
摘要翻译： 完整的浮点矢量处理器包括具有DMA I / O装置的主处理单元，具有静态RAM和/或交错动态RAM的宽带数据存储器，地址发生器，用于为数据存储器中加载的数据提供地址生成， 同时操作的管线控制定序器，其可操作地与由地址发生器产生的地址同步地提供完全可编程的水平格式微指令;以及流水线运算和逻辑单元，其响应于所寻址的数据和同步提供的微指令，并可操作以评估用户可选择的一个 多个计算密集型功能。 地址发生器，管线控制顺序器和主处理单元并行配置。 地址发生器包括用于提供流水线输入和输出数据相关地址生成的装置。 微指令控制的流水线算术和逻辑单元包括两个寄存器文件，其可通过前馈和反馈数据流路径可控地互连，用户可选择的固定或浮点格式乘法器，用户可选择的固定或浮点格式算术和逻辑单元，以及符号锁存器 算术和逻辑单元之间的一个寄存器文件。 符号锁存微指令控制可操作以向算术和逻辑单元提供依赖于数据的分解能力。 微指令控制写地址FIFO和读地址FIFO耦合到数据存储器。
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公开(公告)号：US4024533A
公开(公告)日：1977-05-17
申请号：US594758
申请日：1975-07-10
申请人： Leopold Neumann
发明人： Leopold Neumann
摘要： An analog-to-digitial converter of the dual slope type wherein simultaneous integration of two input signals is achieved to provide a digital output substantially immune to disturbances affecting both signals. First and second dual slope converter circuits are employed, each receiving a respective analog signal. During conversion of the first signal, integration of the second signal is accomplished such that a digital output signal is provided representing the integrated instantaneous ratio of the two input signals and which is substantially free of disturbances affectng both of signals which may be introduced during a conversion cycle.
摘要翻译： 实现双斜率类型的模数转换器，其中实现两个输入信号的同时积分，以提供基本上免受影响两个信号的扰动的数字输出。 采用第一和第二双斜率转换器电路，每个接收相应的模拟信号。 在转换第一信号期间，实现第二信号的积分，使得提供表示两个输入信号的积分瞬时比率的数字输出信号，并且其基本上没有影响可能在转换期间引入的信号的干扰 周期。
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公开(公告)号：US4008405A
公开(公告)日：1977-02-15
申请号：US584052
申请日：1975-06-05
申请人： Leopold Neumann , Bernard M. Gordon
发明人： Leopold Neumann , Bernard M. Gordon
摘要： For use in an electronic digitizer such as employed in an electronic weighing system, a circuit for detecting motion and providing a digital output signal. The circuitry includes a dual slope analog-to-digital converter having means for retaining a representation of the integrated analog level of a present and previous conversion cycle, the levels being representative of sampled data. The stored amplitudes are compared to provide an analog difference signal, and an output signal representative of measured weight is provided only when the difference signal is less than a predetermined reference threshold.
摘要翻译： 用于诸如在电子称重系统中使用的电子数字转换器，用于检测运动并提供数字输出信号的电路。 电路包括双斜率模数转换器，其具有用于保持当前和之前转换周期的集成模拟电平的表示的装置，该电平代表采样数据。 存储的幅度被比较以提供模拟差分信号，并且仅当差信号小于预定参考阈值时才提供表示测量的权重的输出信号。
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公开(公告)号：US11347202B2
公开(公告)日：2022-05-31
申请号：US16011817
申请日：2018-06-19
申请人： Analogic Corporation
发明人： Stephen Glow
IPC分类号： G05B19/414 , G05B19/4155 , G05B19/418
摘要： A servo control module for a motion control system with a plurality of individual servo control modules. The servo control module includes a single axis servo drive. The servo control module further includes a set of input pins configured to receive motor state information of motors controlled by single axis servo drives of all of the other of the plurality of servo control modules over a dedicated inter-drive network each servo update cycle. The servo control module further includes a set of output pins configured to transmit the motor state information of a motor controlled by the single axis servo drive and the received state information over the inter-drive network of motors each servo update cycle.
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公开(公告)号：US20210405242A1
公开(公告)日：2021-12-30
申请号：US17342065
申请日：2021-06-08
申请人： Analogic Corporation
发明人： Steven Weed , Patrick Splinter
摘要： Scanning systems may include a stator, a rotor supporting at least one radiation source and at least one radiation detector rotatable with the rotor, and a motivator operatively connected to the rotor. The stator, the rotor, the at least one radiation source, and the at least one radiation detector may be located within a housing. A conveyor system may extend through the housing and the rotor. A shielding system including a series of independently movable energy shields sized, shaped, and positioned to at least partially occlude a pathway along which the conveyor system extends may extend from an entrance to the housing, through the rotor, to an exit from the housing. A control system may be configured to cause the shielding system to automatically and dynamically move individual energy shields in response to advancement of one or more objects supported on the conveyor system.
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公开(公告)号：US20210353237A1
公开(公告)日：2021-11-18
申请号：US17354951
申请日：2021-06-22
申请人： Analogic Corporation
发明人： Robert Williams , Andrew Alvino , Ronald E Swain , Tadas Vaisvila
摘要： Among other things, a computed tomography (CT) imaging modality is provided. The imaging modality includes a radiation source that emits radiation. The imaging modality includes a detector array that detects at least a portion of the radiation. The imaging modality includes a rotating structure that rotates about an axis. The rotating structure includes a first support portion having a first shape. The rotating structure includes a second support portion having a second shape different than the first shape. The radiation source and the detector array are mounted to the second support portion.
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公开(公告)号：US11129581B2
公开(公告)日：2021-09-28
申请号：US16485764
申请日：2017-02-16
申请人： Analogic Corporation
摘要： Among other things, an anti-scatter collimator is provided including a first layer defining a first retaining member at a first surface. A second layer defines a second retaining member at a first surface that faces the first surface of the first layer. A septum is disposed between the first layer and the second layer and physically contacts the first retaining member and the second retaining member. The first retaining member and the second retaining member maintain a position of the septum relative to the first layer and the second layer. The septum has a third attenuation coefficient that is greater than a first attenuation coefficient of the first layer and a second attenuation coefficient of the second layer. An end support is attached to the first layer and to the second layer. The end support borders an end of the septum.
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