公开(公告)号：US20100221862A1

公开(公告)日：2010-09-02

申请号：US12780832

申请日：2010-05-14

Applicant: Emmanuelle Vigier-Blanc ,  Guillaume Cassar

Inventor： Emmanuelle Vigier-Blanc ,  Guillaume Cassar

IPC: H01L31/02 ,  H01L31/0232 ,  H01L31/0352 ,  H01L21/22

CPC classification number: H01L27/14627 ,  G02B3/0087 ,  G02B13/001 ,  G02B13/0055 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2224/13 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: An imaging optical module is designed to be placed in front of an optical image sensor of a semiconductor component. The module includes at least one element which has a refractive index that varies between its optical axis and its periphery, over at least an annular part and/or over its central part. The element may be a tablet in front of the semiconductor sensor or a lens in front of the semiconductor sensor. The direction of variation in refractive index may be oppositely oriented with respect to the table and lens.

Abstract translation: 成像光学模块被设计为放置在半导体部件的光学图像传感器的前面。 该模块包括至少一个元件，其具有在其光轴和其周边之间，至少在环形部分和/或其中心部分上方的折射率。 元件可以是半导体传感器前面的片剂或半导体传感器前面的透镜。 折射率的变化方向可以相对于台面和透镜相反地取向。

公开(公告)号：US07777289B2

公开(公告)日：2010-08-17

申请号：US11432678

申请日：2006-05-10

Applicant: François Roy ,  Arnaud Tournier

Inventor： François Roy ,  Arnaud Tournier

IPC: H01L27/146

CPC classification number: H01L27/14609 ,  H01L27/1443

Abstract: An integrated circuit includes at least one photodiode of the floating substrate type which is associated with a read transistor. The photodiode is formed from a buried layer lying beneath the floating substrate and an upper layer lying on the floating substrate. The upper layer incorporates the source and drain regions of the read transistor. The source and drain regions are produced on either side of the gate of the read transistor. An isolating trench is located alongside the source region and extends from the upper surface of the upper layer down to below the buried layer, so as to isolate the source region from said buried layer.

Abstract translation: 集成电路包括与读取晶体管相关联的浮置衬底类型的至少一个光电二极管。 光电二极管由位于浮置衬底之下的掩埋层和位于浮动衬底上的上层形成。 上层结合读取晶体管的源极和漏极区域。 源极和漏极区域在读取晶体管的栅极的任一侧上产生。 隔离沟槽位于源极区旁边，并从上层的上表面向下延伸到掩埋层的下方，从而将源极区域与掩埋层隔离。

公开(公告)号：US07773151B2

公开(公告)日：2010-08-10

申请号：US11404575

申请日：2006-04-14

Applicant: Christophe Barnichon

Inventor： Christophe Barnichon

IPC: H04N7/01

CPC classification number: H04N7/012

Abstract: A device and a method of deinterlacing a sequence of images from an interlaced format to a progressive format. The sequence of images being composed of successive frames. A plurality of pixels of missing lines of a current frame to be completed, an evaluation of the values of these pixels according to a spatially consistent order. The evaluation comprises, for each pixel of the plurality of pixels, estimating a direction of interpolation, spatial interpolation according to the estimated direction of interpolation. According to the invention, the estimation step comprises, for at least one current pixel of the plurality of pixels, calculating a score for at least two directions, and selecting the direction of interpolation on the basis of the calculated scores and of the estimated direction of interpolation for a distinct pixel situated in the neighborhood of the current pixel.

Abstract translation: 一种从隔行格式到逐行格式将一系列图像去隔行的装置和方法。 图像序列由连续的帧组成。 要完成的当前帧的缺失行的多个像素，根据空间一致的顺序评估这些像素的值。 评价包括对于多个像素的每个像素，根据估计的内插方向估计插值方向的空间插值。 根据本发明，估计步骤包括：针对多个像素中的至少一个当前像素，计算至少两个方向的分数，并根据所计算出的分数和估计的方向选择插值方向 位于当前像素附近的不同像素的插值。

公开(公告)号：US07769965B2

公开(公告)日：2010-08-03

申请号：US11729308

申请日：2007-03-27

Applicant: Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sébastien Ferroussat

Inventor： Patrice Couvert ,  Xavier Cauchy ,  Anthony Philippe ,  Sébastien Ferroussat

IPC: G06F12/00 ,  G06F17/30

CPC classification number: G06F13/28

Abstract: Data stored in a first memory are processed by a processing device comprising a processor, a second memory, and an interface device interfacing the processing of data from the first memory. In the interface device, in order to facilitate transfer of data from the first memory where data are stored in a first data format to the second memory where data are stored in a second data format, a first group of data is received from the first memory, with said group ordered into a sequence corresponding to the first data format. Then at least one second group of data is obtained by ordering said data in the first group into a new sequence which is a function of the first and second data formats. The second group of data is stored in the second memory.

Abstract translation: 存储在第一存储器中的数据由包括处理器，第二存储器和与来自第一存储器的数据的处理接口的接口设备的处理设备处理。 在接口装置中，为了促进将数据以第一数据格式存储的第一存储器的数据传送到以第二数据格式存储数据的第二存储器，从第一存储器接收第一组数据 ，所述组被排序成对应于第一数据格式的序列。 然后通过将第一组中的所述数据排序成作为第一和第二数据格式的函数的新序列来获得至少一个第二组数据。 第二组数据存储在第二个存储器中。

公开(公告)号：US07768150B2

公开(公告)日：2010-08-03

申请号：US12116846

申请日：2008-05-07

Applicant: Giuseppe Platania ,  Jerome Nebon ,  Patrizia Milazzo ,  Alexandre Balmefrezol ,  Vincenzo Polisi

Inventor： Giuseppe Platania ,  Jerome Nebon ,  Patrizia Milazzo ,  Alexandre Balmefrezol ,  Vincenzo Polisi

IPC: H02J3/38

CPC classification number: H02J7/0065 ,  H02J2007/0062 ,  Y10T307/313 ,  Y10T307/533

Abstract: A power management unit for a battery-operated electronic device having a bus interface for the interconnection with another electronic device, the power management unit including an electric energy storage element coupled between a battery of the battery-operated electronic device and a voltage supply line of the bus interface, the electric energy storage element being operable to charge/discharge electric energy; a drive circuitry arranged to control a charge/discharge of the electric energy storage element. The drive circuitry is operable to cause an electric power supplied by the other electronic device through the voltage supply line to re-charge the battery; or, in case the other electronic device does not supply electric power, cause the battery supply electric power to the other electronic device through the voltage supply line. The power management unit is particularly adapted for battery-operated, mobile USB OTG devices.

Abstract translation: 一种用于电池供电的电子设备的电源管理单元，具有用于与另一电子设备互连的总线接口，所述电源管理单元包括耦合在电池供电的电子设备的电池和电池供电线路之间的电能存储元件 所述总线接口，所述蓄电元件可操作以对电能进行充电/放电; 布置成控制电能存储元件的充电/放电的驱动电路。 所述驱动电路可操作以使由所述另一电子装置通过所述电压供给线提供的电力对所述电池进行再充电; 或者在其他电子设备不供电的情况下，通过电压供给线使电池向另一方的电子设备供电。 电源管理单元特别适用于电池供电的移动USB OTG设备。

公开(公告)号：US07751793B2

公开(公告)日：2010-07-06

申请号：US11294802

申请日：2005-12-06

Applicant: Armand Castillejo ,  Fabienne Rerat

Inventor： Armand Castillejo ,  Fabienne Rerat

IPC: H04B1/26 ,  H01F5/00

CPC classification number: H01F21/12 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit including a structure of inductances on a semiconductor substrate, intended for operating at frequencies greater than several hundreds of MHz, including a first inductance formed by a conductive track and having first and second terminals respectively connected to each of the two ends of the conductive track, including a second inductance formed by the conductive track between the second terminal and any intermediary point of the conductive track connected to a third terminal, said second and third terminals forming the two terminals of the second inductance, and means for setting the third terminal to high impedance when the first inductance is used.

Abstract translation: 一种集成电路，包括在半导体衬底上的电感结构，用于在大于几百MHz的频率下工作，包括由导电轨迹形成的第一电感，并具有分别连接到导电轨道的两端的第一和第二端子 导电轨道，包括由第二端子和连接到第三端子的导电轨道的任何中间点之间的导电轨迹形成的第二电感，所述第二和第三端子形成第二电感的两个端子，以及用于设置第三电感的装置 当使用第一电感时端子到高阻抗。

公开(公告)号：US07739566B2

公开(公告)日：2010-06-15

申请号：US11698249

申请日：2007-01-24

Applicant: Paul Armagnat

Inventor： Paul Armagnat

IPC: G01R31/28 ,  G06F3/00

CPC classification number: G01R31/318555

Abstract: An electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of the circuit which is dedicated to the state machine to the devices relating to scan testing. The state machine supports a plurality of data transfer protocols. The choice of the protocol to be used is made as a function of a signal received on the input pin. Responsive to an input pin signal, the state machine enters an operational mode wherein scan test programming data is serially received at the input pin and communicated to the devices which facilitate scan testing. More specifically, the scan test programming data is serially communicated to a scan test register, where the data is output in parallel to the scan test device.

Abstract translation: 电子电路包括一组便于扫描测试电子电路的至少一部分的装置。 这些设备包括扫描测试设备。 电路还包括状态机，其操作以将数据从专用于状态机的电路的输入引脚传送到与扫描测试有关的设备。 状态机支持多个数据传输协议。 要使用的协议的选择是根据在输入引脚上接收的信号的函数。 响应于输入引脚信号，状态机进入操作模式，其中扫描测试编程数据在输入引脚处串行接收并传送到便于扫描测试的器件。 更具体地，扫描测试编程数据被串行地传送到扫描测试寄存器，其中数据与扫描测试设备并行输出。

公开(公告)号：US07734672B2

公开(公告)日：2010-06-08

申请号：US11166565

申请日：2005-06-24

Applicant: Pierre-Yvan Liardet ,  Yannick Teglia

Inventor： Pierre-Yvan Liardet ,  Yannick Teglia

IPC: G06F1/02

CPC classification number: H03K3/84

Abstract: A method and a circuit for detecting a possible loss of the equiprobable character of a first output bit flow originating from at least one first normalization element of an initial bit flow, consisting of submitting the initial flow to at least one second normalization element of a nature different from the first one, pairing, bit to bit, the flows originating from the two elements, and checking the equidistribution of the different state pairs.

Abstract translation: 一种用于检测源自初始比特流的至少一个第一归一化元素的第一输出比特流的等能特性的可能损失的方法和电路，其包括将初始流提交给自然的至少一个第二归一化元素 与第一个不同，配对，比特，比特，来自两个元素的流，以及检查不同状态对的等分布。

公开(公告)号：US20100135427A1

公开(公告)日：2010-06-03

申请号：US12696069

申请日：2010-01-29

Applicant: Nicole Alcouffe

Inventor： Nicole Alcouffe

IPC: H04K1/10 ,  H04J11/00

CPC classification number: H04L27/2662 ,  H04L25/022 ,  H04L27/2607 ,  H04L27/2665

Abstract: The invention relates to a method for the COFDM demodulation of a signal received from a transmission channel. The inventive method includes performing the fast Fourier transform of the signal received in a window corresponding to a symbol, each symbol being associated with a guard time reproducing one part of the symbol; supplying a set of estimated values for the module impulse response; determining coefficients, each coefficient being obtained from the product of the aforementioned set and a filtering function (FE) for a determined relative position of the filtering function in relation to the set; determining the maximum coefficient and the corresponding relative position; and positioning the window as a function of the relative position, the filtering function including a central part (LMAX) which has a constant amplitude and a duration equal to the duration of the guard time and which is surrounded by non-zero decreasing edges.

Abstract translation: 本发明涉及从传输信道接收的信号进行COFDM解调的方法。 本发明的方法包括对与一符号对应的窗口中接收的信号执行快速傅立叶变换，每个符号与再现该符号的一部分的保护时间相关联; 为模块脉冲响应提供一组估计值; 确定系数，根据上述集合的乘积和滤波函数（FE）获得的每个系数针对所确定的过滤函数相对于该集合的相对位置; 确定最大系数和相应的相对位置; 并且根据所述相对位置将所述窗口定位，所述滤波功能包括中心部分（LMAX），所述中心部分具有恒定的幅度和持续时间等于所述保护时间的持续时间并被非零减少边缘包围。

公开(公告)号：US20100135087A1

公开(公告)日：2010-06-03

申请号：US12699134

申请日：2010-02-03

Applicant: Sylvie Wuidart

Inventor： Sylvie Wuidart

IPC: G11C7/06

CPC classification number: G11C7/06 ,  G11C2207/066

Abstract: A method for reading of the state of a non-volatile memory element including conditioning the frequency of a first oscillator to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator, selected between two possible frequency values for the first oscillator, according to the state of the storage element.

Abstract translation: 一种用于读取非易失性存储元件的状态的方法，包括将第一振荡器的频率调节到该元件的状态，并将第一振荡器的频率与第二振荡器的预定频率进行比较，所述第二振荡器的频率在两个可能的 根据存储元件的状态，第一振荡器的频率值。