公开(公告)号：US20090031173A1

公开(公告)日：2009-01-29

申请号：US12206967

申请日：2008-09-09

Applicant: Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

Inventor： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/2268 ,  G06F11/3476 ,  G06F11/348

Abstract: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

Abstract translation: 在处理器中公开了一种方法，装置和计算机程序产品，用于在运行时期间动态地为存储器内硬件跟踪分配存储器。 处理器包含在数据处理系统中。 处理器包括使用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控​​制器。 确定存储跟踪数据所需的特定大小的系统存储器。 硬件跟踪设施在数据处理系统完成启动之后动态地请求要分配给硬件跟踪设备的系统内存的特定大小，用于存储由硬件跟踪设备捕获的跟踪数据。 固件选择系统内存中的特定位置。 所有特定位置在一起是特定的尺寸。 固件分配由硬件跟踪设备专门使用的特定位置。

公开(公告)号：US07480833B2

公开(公告)日：2009-01-20

申请号：US11779561

申请日：2007-07-18

Applicant: Michael Billeci ,  Timothy J. Slegal

Inventor： Michael Billeci ,  Timothy J. Slegal

IPC: G06F11/00

CPC classification number: G06F11/2268

Abstract: Methods and systems for pre-detecting a hardware hang in a processor. The methods comprise maintaining a count of a number of cycles in a predefined time interval without an instruction being completed; detecting a pre-hang condition if said count is within N counts of a hang limit; initiating trace capture in response to detecting said pre-hang condition; and detecting a hang condition if said count equals said hang limit.

Abstract translation: 用于预检测处理器中的硬件挂起的方法和系统。 所述方法包括在预定义的时间间隔内保持多个周期的计数，而不完成指令; 如果所述计数在暂停限制的N个计数内，则检测预挂起状态; 响应于检测到所述预悬挂条件而启动跟踪捕获; 并且如果所述计数等于所述挂起限制，则检测挂起状况。

公开(公告)号：US20090006896A1

公开(公告)日：2009-01-01

申请号：US12230241

申请日：2008-08-26

Applicant: Masato Nakagawa

Inventor： Masato Nakagawa

IPC: G06F11/07

CPC classification number: G06F11/2268 ,  G06F11/079

Abstract: Relating with board numbers of the boards mounted with the logic circuits and mounted places on the boards and in relation to log information to be collected from the logic circuits, analysis information describing information to be processed when the log information is generated, information of a condition for which the log information is to be valid, and information of a condition for which the log information is to be invalid are defined for analyzing failures using the analysis information based on the logic circuits. Upon the realization of the failure analysis based on the logic circuits, the analysis information further describes information of the priority of the log information to realize a thorough analysis of critical failures.

Abstract translation: 关于安装有逻辑电路的板的板号和板上的安装位置以及从逻辑电路收集的日志信息，描述当生成日志信息时要处理的信息的分析信息，条件信息 定义日志信息有效的日志信息的信息和日志信息无效的条件的信息，用于基于逻辑电路使用分析信息来分析故障。 在实现基于逻辑电路的故障分析时，分析信息进一步描述了日志信息的优先级信息，以实现关键故障的彻底分析。

公开(公告)号：US20080282226A1

公开(公告)日：2008-11-13

申请号：US11745389

申请日：2007-05-07

Applicant: Carli Connally ,  Bryan Carpenter

Inventor： Carli Connally ,  Bryan Carpenter

IPC: G06F9/44

CPC classification number: G06F11/2268

Abstract: In one embodiment, a computer determines a plurality of data types associated with different ones of a plurality of test data items, and based on the determined data types, i) logs a first set of the plurality of test data items to volatile storage, and ii) logs a second set of the plurality of test data items to nonvolatile storage. The computer also monitors a current state of a graphical user interface (GUI). When the current state of the GUI is one of a first number of GUI states, the computer displays via the GUI, a dynamically updated set of test data items derived from the volatile storage. When the current state of the GUI is one of a second number of GUI states, the computer displays, via the GUI, a dynamically updated set of test data items derived from the nonvolatile storage. Other embodiments are also disclosed.

Abstract translation: 在一个实施例中，计算机确定与多个测试数据项中的不同测试数据项相关联的多个数据类型，并且基于所确定的数据类型，i）将多个测试数据项的第一组日志记录到易失性存储器，以及 ii）将第二组多个测试数据项记录到非易失性存储器。 计算机还监视图形用户界面（GUI）的当前状态。 当GUI的当前状态是GUI状态的第一数量之一时，计算机经由GUI显示从易失性存储器导出的动态更新的测试数据项集。 当GUI的当前状态是第二数量的GUI状态之一时，计算机经由GUI显示从非易失性存储器导出的动态更新的测试数据项集。 还公开了其他实施例。

公开(公告)号：US07437617B2

公开(公告)日：2008-10-14

申请号：US11055845

申请日：2005-02-11

Applicant: Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

Inventor： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC: G06F11/00

CPC classification number: G06F11/2268 ,  G06F11/348

Abstract: A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.

Abstract translation: 公开了一种方法，装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。 硬件跟踪设备捕获处理器中的硬件跟踪数据。 硬件跟踪工具包含在处理器内。 使用系统总线将硬件跟踪数据传输到系统存储器。 系统内存包含在系统中。 当将硬件跟踪数据发送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。 系统内存的一部分用于存储跟踪数据。 系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。

公开(公告)号：US20080141077A1

公开(公告)日：2008-06-12

申请号：US11634500

申请日：2006-12-06

Applicant: Robert C. Swanson ,  Michael A. Rothman ,  Mallik Bulusu ,  Vincent J. Zimmer

Inventor： Robert C. Swanson ,  Michael A. Rothman ,  Mallik Bulusu ,  Vincent J. Zimmer

IPC: G06F11/00

CPC classification number: G06F11/2268 ,  G06F11/008

Abstract: In some embodiments, the invention involves a system and method to continuously log correctable errors without rebooting by changing the granularity of the error detection and logging mechanism. A mask register is used to identify which errors are to be logged. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，本发明涉及通过改变错误检测和记录机制的粒度来连续记录可纠正错误而不重新启动的系统和方法。 掩码寄存器用于识别要记录哪些错误。 描述和要求保护其他实施例。

公开(公告)号：US07346813B1

公开(公告)日：2008-03-18

申请号：US10818203

申请日：2004-04-05

Applicant: Jürgen M. Schulz ,  David L. Isaman

Inventor： Jürgen M. Schulz ,  David L. Isaman

IPC: G06F11/00

CPC classification number: G06F11/2268 ,  G06F11/2736

Abstract: In one embodiment, an apparatus comprises a plurality of core logic blocks, a plurality of first event blocks, and a second event block. Each of the plurality of core logic blocks is configured to generate one or more indications of one or more events. Each first event block of the plurality of first event blocks is coupled to a respective core logic block of the plurality of core logic blocks to receive the one or more indications from the respective core logic block. Each first event block comprises at least one register configured to record which events have been indicated by the respective core logic block. Coupled to the plurality of first event blocks, the second event block is configured to initiate one or more actions responsive to one or more events detected in one or more of the plurality of first event blocks.

Abstract translation: 在一个实施例中，装置包括多个核心逻辑块，多个第一事件块和第二事件块。 多个核心逻辑块中的每一个被配置为生成一个或多个事件的一个或多个指示。 多个第一事件块中的每个第一事件块被耦合到多个核心逻辑块的相应核心逻辑块以从相应的核心逻辑块接收一个或多个指示。 每个第一事件块包括至少一个寄存器，其被配置为记录哪些事件已被相应的核心逻辑块指示。 耦合到多个第一事件块，第二事件块被配置为响应于在多个第一事件块中的一个或多个中检测到的一个或多个事件发起一个或多个动作。

公开(公告)号：US20080016409A1

公开(公告)日：2008-01-17

申请号：US11779561

申请日：2007-07-18

Applicant: Michael Billeci ,  Timothy Slegel

Inventor： Michael Billeci ,  Timothy Slegel

IPC: G06F11/00

CPC classification number: G06F11/2268

Abstract: Methods and systems for pre-detecting a hardware hang in a processor. The methods comprise maintaining a count of a number of cycles in a predefined time interval without an instruction being completed; detecting a pre-hang condition if said count is within N counts of a hang limit; initiating trace capture in response to detecting said pre-hang condition; and detecting a hang condition if said count equals said hang limit.

Abstract translation: 用于预检测处理器中的硬件挂起的方法和系统。 所述方法包括在预定义的时间间隔内保持多个周期的计数，而不完成指令; 如果所述计数在暂停限制的N个计数内，则检测预挂起状态; 响应于检测到所述预悬挂条件而启动跟踪捕获; 并且如果所述计数等于所述挂起限制，则检测挂起状况。

公开(公告)号：US20060218444A1

公开(公告)日：2006-09-28

申请号：US11188690

申请日：2005-07-25

Applicant: Masahiro Yoshida ,  Takeshi Obata ,  Taichi Ohno

Inventor： Masahiro Yoshida ,  Takeshi Obata ,  Taichi Ohno

IPC: G06F11/00

CPC classification number: G06F11/2268

Abstract: A log management module 10 acquires log data from a computer, temporarily stores the log data in a buffer, and writes the stored log data into a disk device 30a. When the log management module 10 detects a failure in the computer, the log management module 10 stops writing log data in the disk device 30a, and writes log data acquired after the failure is detected in a disk device 30b.

Abstract translation: 日志管理模块10从计算机获取日志数据，将日志数据临时存储在缓冲器中，并将存储的日志数据写入盘装置30a。 当日志管理模块10检测到计算机中的故障时，日志管理模块10停止在盘装置30a中写入日志数据，并且将在故障之后获取的日志数据写入到盘装置30b中。

公开(公告)号：US06934891B2

公开(公告)日：2005-08-23

申请号：US09907618

申请日：2001-07-19

Applicant: Masahiro Kawaguchi ,  Shizuo Yokohata ,  Shinichi Nakayama ,  Youichi Goto

Inventor： Masahiro Kawaguchi ,  Shizuo Yokohata ,  Shinichi Nakayama ,  Youichi Goto

IPC: G06F12/08 ,  G06F3/06 ,  G06F11/22 ,  G06F11/34 ,  G06F13/00 ,  G06F11/00

CPC classification number: G06F11/348 ,  G06F11/2268 ,  G06F11/349

Abstract: A storage system includes a storage controller connected to higher-level devices and a plurality of storages connected to the storage controller for storing data from the higher-level devices. The storage controller includes a channel controller for establishing interface for the higher-level devices, the channel controller including trace information representing details of the interface, and storages for storing the trace information from the channel controller in a format which can be accessed by the higher-level devices. In this configuration, when the channel controller receives a trace information fetching indication from one of the higher-level devices, the channel controller transfers trace information to a cache memory and the storages or to the cache memory or the storages.

Abstract translation: 存储系统包括连接到更高级设​​备的存储控制器和连接到存储控制器的多个存储器，用于存储来自较高级别设备的数据。 存储控制器包括用于建立更高级设备的接口的信道控制器，信道控制器包括表示接口细节的跟踪信息，以及用于以通道控制器的格式存储跟踪信息的存储器，其格式可由较高级 级设备。 在该配置中，当信道控制器从上级设备之一接收跟踪信息取出指示时，信道控制器将跟踪信息传送到高速缓冲存储器以及存储器或高速缓冲存储器或存储器。