公开(公告)号：US4761733A

公开(公告)日：1988-08-02

申请号：US710615

申请日：1985-03-11

Applicant: Andrew J. McCrocklin ,  Nicholas E. Aneshansley ,  Patricia Shanahan ,  James J. Whelan ,  Jeffrey P. Anderson ,  James E. Kocol ,  Gary L. Riddle

Inventor： Andrew J. McCrocklin ,  Nicholas E. Aneshansley ,  Patricia Shanahan ,  James J. Whelan ,  Jeffrey P. Anderson ,  James E. Kocol ,  Gary L. Riddle

IPC: G06F9/22 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1063 ,  G06F12/0875 ,  G06F9/22

Abstract: A direct-execution microprogrammable microprocessor system uses an emulatory microprogrammable microprocessor for direct execution of microinstructions in main memory through a microinstruction port. A microinstruction cache with a microinstruction address extension unit serving to communicate microinstructions from the main memory to the microprogrammable microprocessor. Virtual main memory accesses occur through a system multiplexer. A virtual address extension unit and a virtual address bus provide extension and redefinition of the main memory address space of the microprogrammable microprocessor. The system also uses a context switching stack cache and an expanded address translation cache with the microprogrammable microprocessor having a reduced and redefined microinstruction set with a variable microinstruction cycle.

Abstract translation: 直接执行微程序微处理器系统使用可编程微程序微处理器来通过微指令端口直接执行主存储器中的微指令。 具有微指令地址扩展单元的微指令缓存，用于将从主存储器的微指令传送到微程序微处理器。 虚拟主存储器访问通过系统多路复用器进行。 虚拟地址扩展单元和虚拟地址总线提供微程序微处理器的主存储器地址空间的扩展和重新定义。 该系统还使用上下文切换堆栈高速缓存和扩展的地址转换高速缓存，其中微程序微处理器具有具有可变微指令周期的简化和重新定义的微指令集。

公开(公告)号：US4419726A

公开(公告)日：1983-12-06

申请号：US225701

申请日：1981-01-16

Applicant: Albert J. Weidner

Inventor： Albert J. Weidner

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/36 ,  G06F9/42

CPC classification number: G06F9/265 ,  G06F9/22

Abstract: An instruction decoding system for data processing apparatus in which alternative instruction interpretations are made possible through hardware sensing of the operational state of one or more machine elements. In one embodiment, a zero detect unit is used to sense the state of a subroutine stack used in a microprogrammed system, therefore permitting a generic "exit" microcommand to be interpreted either as a "return" or a "decode" depending upon the state of the subroutine stack.

Abstract translation: 一种用于数据处理装置的指令解码系统，其中通过对一个或多个机器元件的操作状态的硬件感测来实现替代指令解释。 在一个实施例中，使用零检测单元来感测在微程序系统中使用的子程序堆栈的状态，因此允许通用的“退出”微命令被视为取决于状态的“返回”或“解码” 的子程序堆栈。

公开(公告)号：US3594730A

公开(公告)日：1971-07-20

申请号：US3594730D

申请日：1968-06-07

Applicant: BELL TELEPHONE LABOR INC

Inventor： TOY WING N

IPC: G06F9/22 ,  G06F11/08 ,  G06F5/00

CPC classification number: G06F9/22 ,  G06F11/085

Abstract: An information processing system characterized by modularity of design and good maintenance features includes a plurality of oneout-of-N translators each of which includes double-output detection circuitry. Some of the translators are operated in a conventional manner to convert a multidigit input word into energization of one particular one of N output lines emanating therefrom. Others of the translators are supplied with periodic clock signals, steady-state reference signals and instruction signals. In response to such a set of signals, these other translators are operated in a unique manner to provide a specified plurality of sequential control signals which are applied to a matrix array to cause the readout therefrom of a corresponding plurality of stored words.

公开(公告)号：US3405258A

公开(公告)日：1968-10-08

申请号：US44618465

申请日：1965-04-07

Applicant: IBM

Inventor： GODOY HUMBERT C ,  GROSS NORMAN E

IPC: G06F9/22 ,  G06F11/267

CPC classification number: G06F11/2215 ,  G06F9/22 ,  G06F9/226

公开(公告)号：US3388381A

公开(公告)日：1968-06-11

申请号：US24882562

申请日：1962-12-31

Applicant: NAVY USA

Inventor： PRYWES NOAH S ,  SAMUEL LITWIN ,  GRAY JR HARRY J

IPC: G06F9/22 ,  G06F9/40 ,  G06F15/78 ,  G06F15/80 ,  G06F17/30

CPC classification number: G06F17/30961 ,  G06F9/22 ,  G06F9/4425 ,  G06F15/78 ,  G06F15/8038 ,  Y10S707/99933

公开(公告)号：US3242465A

公开(公告)日：1966-03-22

申请号：US15673961

申请日：1961-12-04

Applicant: RCA CORP

Inventor： ELI GLOATES ,  RAKOCZI LASZLO L

IPC: G06F9/22 ,  G06F9/40 ,  G06F15/78 ,  G06F15/80

CPC classification number: G06F9/4425 ,  G06F9/22 ,  G06F15/7896 ,  G06F15/8007

Abstract: 1,010,179. Electric digital computers. RADIO CORPORATION OF AMERICA. Nov. 22, 1962 [Dec. 4, 1961], No. 44249/62. Heading G4A. A data processing system includes a basic data processing system having an instruction register and an instruction decoder, and a supplemental data processing system having an instruction decoder responsive to words in the basic system instruction register, control of operations for the entire system being transferred to the supplemental instruction decoder when an instruction is decoded thereby. A flexible system comprising a basic system to which a variable number of supplemental systems may be added is thus provided, the supplemental systems being capable of performing additional operations or of overriding certain of the basic system operations. Basic system.-A basic system Sa, Fig. 3, includes a memory 300 and an instruction register 10a, the contents of the operations portion of which is referred to as an " operations word ". In the basic system 8a, an instruction decoder 12a applies signals to a machine instruction generator 18a which produces a sequence of signals for each operations word, each of these signals causing a bit pattern generator 20a to produce a sequence of bit patterns which are applied to a bit pattern register 22. The output of the register 22 is applied to a bit pattern decoder 24 which produces one or more command signals for each bit pattern, the command signals being applied to the arithmetic unit and other networks 23 in the basic system. When a circuit which has received a command completes its function, it produces an output signal, called a " return ", which is applied to " return " sensing circuit 27 which produces outputs to clear the bit pattern register 22 thereby causing the bit pattern generator 20a to apply a new pattern to the register 22. Supplemental systems.-To the basic system 8a, there may be added one or more additional systems 8b. The system 8b contains an instruction decoder 12b responsive to certain operations words in the instruction register 10a and connected to a machine instruction generator 18b whose output is applied to a bit pattern generator 20b connected to the bit pattern register 22 in the basic system 8a, thereby producing command signals via the decoder 24 for the arithmetic units and other networks 23, 23b, 23c in any supplemental systems which are connected to the basic system. When the instruction decoder 12b is activated it causes inhibit circuits 31b to inhibit the machine instruction generator 18a in the basic system. Circuit details.-The circuits in each system for the machine instruction generator, bit pattern generator, bit pattern register and bit pattern decoder, which consist of arrangements of gates and flip-flops, are described in detail in the Specification (Figs. 6-8, not shown).

公开(公告)号：US12124418B2

公开(公告)日：2024-10-22

申请号：US17132741

申请日：2020-12-23

Applicant: Citrix Systems, Inc.

Inventor： Wenshuang Zhang ,  Gaojun Chen

IPC: G06F16/00 ,  G06F9/455 ,  G06F16/21 ,  G06F9/22

CPC classification number: G06F16/212 ,  G06F9/45558 ,  G06F9/22 ,  G06F2009/45562

Abstract: Methods and systems for generating recommendations for microapps are described herein. A plurality of microapps may be provided to a user to subscribe to (e.g., use). The user may have difficulty determining, from among the plurality of microapps, which microapps the user may want to use. To improve user experience, microapp recommendations may be sent to the user to assist the user in determining which microapps to use. The microapp recommendations may be based on correlation levels determined between pairs of microapps.

公开(公告)号：US20230359581A1

公开(公告)日：2023-11-09

申请号：US17842129

申请日：2022-06-16

Applicant: EIDETIC COMMUNICATIONS INC.

Inventor： Sean Gregory GIBB ,  Saeed FOULADI FARD

IPC: G06F9/30 ,  G06F9/22

CPC classification number: G06F9/30185 ,  G06F9/30178 ,  G06F9/22

Abstract: A system, and associated method, includes a plurality of data processing units, a target CPU, an interconnect unit that is separate from the target CPU and configured to receive a data payload and a prefix that includes a sequentially ordered list of the processing units that will perform the data operations and the sets of parameters to be used by each of the processing units, and based on the sequentially ordered list, the interconnect unit sends the data payload to a first processing unit, and receives back processed data, then sends the processed data to the subsequent processing unit, and receives back further processed data, and so forth until all of the data operations have been performed by the processing units set forth in the sequentially ordered list.

公开(公告)号：US20190205163A1

公开(公告)日：2019-07-04

申请号：US15860708

申请日：2018-01-03

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Kamlesh Pillai ,  James Valerio ,  Joydeep Ray ,  Abhishek Appu

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/22 ,  G06T1/20

CPC classification number: G06F9/4881 ,  G06F9/22 ,  G06F9/54 ,  G06T1/20 ,  G06T15/005

Abstract: A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.

公开(公告)号：US20180011755A1

公开(公告)日：2018-01-11

申请号：US15712903

申请日：2017-09-22

Applicant: FUJITSU LIMITED

Inventor： Hiroshi SAKURAI

IPC: G06F11/07 ,  G06F9/22 ,  G06F11/14 ,  G06F13/10

CPC classification number: G06F11/0727 ,  G06F9/22 ,  G06F11/004 ,  G06F11/14 ,  G06F11/141 ,  G06F11/221 ,  G06F13/10

Abstract: It is provided an information processing apparatus. The information processing apparatus includes memory, a processor configured to control a device, a circuit connected with the memory, the processor and the device and configured to store a first sequence which causes a failure of the device in a first storage area in the memory, store a second sequence which prevents the failure in a second storage area in the memory, determine whether a third sequence for controlling the device included in a packet output from the processor is the first sequence, coordinate the third sequence by using the second sequence when the third sequence is the first sequence, and generate a packet including the coordinated third sequence.