公开(公告)号：US06976051B1

公开(公告)日：2005-12-13

申请号：US10003724

申请日：2001-11-14

申请人： Ozan E. Erdogan ,  Cormac Conroy

发明人： Ozan E. Erdogan ,  Cormac Conroy

IPC分类号： G06G7/02

CPC分类号： H03H11/22 ,  H03H2011/0494

摘要： A complex filter includes an I channel having a first I channel output and a second I channel output and a Q channel having a first Q channel output and a second Q channel output. The second I channel output is input to the Q channel through a first passive network and wherein the second Q channel output is input to the I channel through a second passive network.

摘要翻译： 复数滤波器包括具有第一I信道输出和第二I信道输出的I信道和具有第一Q信道输出和第二Q信道输出的Q信道。 第二I通道输出通过第一无源网络输入到Q通道，并且其中第二Q通道输出通过第二无源网络输入到I通道。

公开(公告)号：US20050265483A1

公开(公告)日：2005-12-01

申请号：US10854027

申请日：2004-05-25

申请人： Ozan Erdogan

发明人： Ozan Erdogan

IPC分类号： H03D1/04 ,  H03D3/00

CPC分类号： H03D3/006

摘要： A communications system comprises a local oscillator configured to generate a local oscillator output and a signal processing component coupled to the local oscillator. The signal processing component is configured to receive a clock signal and the clock signal is derived from the local oscillator output. A method of demodulating an input signal comprises deriving a conversion signal from a local oscillator output, deriving a clock signal from the local oscillator output, mixing the input signal with the conversion signal to generate an intermediate frequency signal, and processing the intermediate frequency signal using a signal processing component driven by the clock signal. A method of modulating an input signal comprise deriving a conversion signal from a local oscillator output, deriving a clock signal from the local oscillator output, processing the input signal using a signal processing component driven by the clock signal to generate an intermediate frequency signal and mixing the intermediate frequency signal with the conversion signal to generate a modulated signal.

摘要翻译： 通信系统包括被配置为产生本地振荡器输出的本地振荡器和耦合到本地振荡器的信号处理部件。 信号处理部件被配置为接收时钟信号，并且时钟信号从本地振荡器输出导出。 解调输入信号的方法包括从本地振荡器输出导出转换信号，从本地振荡器输出导出时钟信号，将输入信号与转换信号混合以产生中频信号，并使用 由时钟信号驱动的信号处理部件。 调制输入信号的方法包括从本地振荡器输出导出转换信号，从本地振荡器输出导出时钟信号，使用由时钟信号驱动的信号处理分量来处理输入信号，以产生中频信号和混频 具有转换信号的中频信号以产生调制信号。

公开(公告)号：US06952126B2

公开(公告)日：2005-10-04

申请号：US10438178

申请日：2003-05-13

申请人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0895

摘要： A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

摘要翻译： 公开了一种用于提供用于锁相环（PLL）的电荷泵电路的技术，以减少上/下电流的失配和上/下电流的馈通到电压输出。 可以通过使用基于电荷泵中的直流参考电压的差分开关（M 1和M 2，以及M 3和M 4）来消除输入信号的馈通，并且还消除了电荷泵中的上/下电流的失配 通过使用反馈应用新的副本偏移来实现宽电压输出范围。

公开(公告)号：US20070004453A1

公开(公告)日：2007-01-04

申请号：US11352438

申请日：2006-02-10

申请人： Beomsup Kim ,  Cormac Conroy

发明人： Beomsup Kim ,  Cormac Conroy

IPC分类号： H04B1/38 ,  H04M1/00

CPC分类号： H04B1/0003 ,  H04B1/005 ,  H04B1/406

摘要： A multistandard RF transceiver is disclosed that may optionally include selectable mixers; selectable amplifiers; a configurable analog filter; and a configurable analog to digital converter. The multistandard RF transceiver may also include a data interface for sending data to a host controller and a control interface for receiving configuration commands from the host controller. The configuration commands identify a wireless standard that is to be implemented by the RF receiver. An RF processor processes an RF signal wherein the processed RF signal is output to the host controller on the data interface.

摘要翻译： 公开了一种多标准射频收发器，其可选地包括可选择的混频器; 可选放大器; 可配置的模拟滤波器; 和可配置的模数转换器。 多标准RF收发器还可以包括用于向主机控制器发送数据的数据接口和用于从主机控制器接收配置命令的控制接口。 配置命令标识要由RF接收机实现的无线标准。 RF处理器处理RF信号，其中处理的RF信号被输出到数据接口上的主机控制器。

公开(公告)号：US20060091966A1

公开(公告)日：2006-05-04

申请号：US11301859

申请日：2005-12-12

申请人： Beomsup Kim ,  Ozan Erdogan ,  Dennis Yee

发明人： Beomsup Kim ,  Ozan Erdogan ,  Dennis Yee

IPC分类号： H03K3/03

CPC分类号： H03L7/24 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1262 ,  H03B5/1296

摘要： A phase synchronous multiple LC tank oscillator is described. A plurality of oscillator stages are configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same and the plurality of oscillators are inductively coupled.

摘要翻译： 描述了一个相位同步多LC波形振荡器。 多个振荡器级被配置为同步振荡。 多个振荡器级中的每一个的相位基本相同，并且多个振荡器被感应耦合。

公开(公告)号：US20040004500A1

公开(公告)日：2004-01-08

申请号：US10438178

申请日：2003-05-13

申请人： Berkana Wireless, Inc.

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L007/06

CPC分类号： H03L7/0895

摘要： A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

摘要翻译： 公开了一种用于提供用于锁相环（PLL）的电荷泵电路的技术，以减少上/下电流的失配和上/下电流的馈通到电压输出。 可以通过使用基于电荷泵中的直流参考电压的差分开关（M1和M2，以及M3和M4）来消除输入信号的馈通，并且还消除宽电压输出中的上/下电流不匹配 通过使用反馈应用新的副本偏移量来实现。

公开(公告)号：US20060208809A1

公开(公告)日：2006-09-21

申请号：US11083180

申请日：2005-03-17

申请人： Ozan Erdogan

发明人： Ozan Erdogan

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/10 ,  H03L7/197

摘要： A precharge circuit that initializes an electronic filter to a middle voltage level of an operational voltage includes a filter isolation device, a filter communication device, and an initializing device. The filter isolation device isolates the electronic filter from electronic circuits connected to an input and an output of the electronic filter to segregate the electronic filter from the electronic circuits connected to the input and the output of the electronic filter during a precharge time. The filter communication device allows communication between the precharge circuit and the electronic filter for initializing the charge state during the precharge time. The initializing device provides an initializing signal to the charge state of the electronic filter during the precharge time. The precharge circuit further has a biasing device in communication with the initializing device to provide a mid level control signal providing a reference level of the charge state.

摘要翻译： 将电子滤波器初始化为工作电压的中间电压电平的预充电电路包括滤波器隔离装置，滤波器通信装置和初始化装置。 滤波器隔离装置将电子滤波器与连接到电子滤波器的输入和输出的电子电路隔离，以在预充电时间期间将电子滤波器与连接到电子滤波器的输入和输出的电子电路隔离。 滤波器通信装置允许预充电电路和电子滤波器之间的通信，用于在预充电时间期间初始化充电状态。 初始化装置在预充电时间期间为电子滤波器的充电状态提供初始化信号。 预充电电路还具有与初始化装置通信的偏置装置，以提供提供充电状态的参考电平的中间电平控制信号。

公开(公告)号：US06844761B2

公开(公告)日：2005-01-18

申请号：US10437417

申请日：2003-05-12

申请人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L2207/14

摘要： A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

摘要翻译： 公开了一种系统和方法，用于为DLL提供假锁定保护器以避免假锁并确保准确的锁定。 假锁定保护器在操作期间从输入参考时钟和输出时钟的信号之间的初始延迟时间超过锁定范围时操作。 具有假锁定保护器的DLL包括参考时钟，由串联连接的多个延迟单元组成的延迟线，用于比较来自参考和输出时钟的信号的相位的相位检测器，比较器，用于控制延迟的延迟的控制器 延迟线。

公开(公告)号：US20040000937A1

公开(公告)日：2004-01-01

申请号：US10437417

申请日：2003-05-12

申请人： Berkana Wireless, Inc.

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L007/06

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L2207/14

摘要： A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

摘要翻译： 公开了一种系统和方法，用于为DLL提供假锁定保护器以避免假锁并确保准确的锁定。 假锁定保护器在操作期间从输入参考时钟和输出时钟的信号之间的初始延迟时间超过锁定范围时操作。 具有假锁定保护器的DLL包括参考时钟，由串联连接的多个延迟单元组成的延迟线，用于比较来自参考和输出时钟的信号的相位的相位检测器，比较器，用于控制延迟的延迟的控制器 延迟线。

公开(公告)号：US20030117201A1

公开(公告)日：2003-06-26

申请号：US10245823

申请日：2002-09-16

申请人： Berkana Wireless, Inc.

发明人： Sung-ho Wang

IPC分类号： H03K003/00

CPC分类号： H03B27/00 ,  H03H7/21 ,  H03H2007/0192

摘要： A quadrature signal generator includes a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop; and a phase corrector that variably controls the capacitance of the variable capacitive elements.

摘要翻译： 正交信号发生器包括多相滤波器，其中四个电阻元件和四个可变电容元件串联交替地形成环路; 以及可变地控制可变电容元件的电容的相位校正器。