公开(公告)号：US06844761B2

公开(公告)日：2005-01-18

申请号：US10437417

申请日：2003-05-12

申请人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L2207/14

摘要： A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

摘要翻译： 公开了一种系统和方法，用于为DLL提供假锁定保护器以避免假锁并确保准确的锁定。 假锁定保护器在操作期间从输入参考时钟和输出时钟的信号之间的初始延迟时间超过锁定范围时操作。 具有假锁定保护器的DLL包括参考时钟，由串联连接的多个延迟单元组成的延迟线，用于比较来自参考和输出时钟的信号的相位的相位检测器，比较器，用于控制延迟的延迟的控制器 延迟线。

公开(公告)号：US06952126B2

公开(公告)日：2005-10-04

申请号：US10438178

申请日：2003-05-13

申请人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0895

摘要： A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

摘要翻译： 公开了一种用于提供用于锁相环（PLL）的电荷泵电路的技术，以减少上/下电流的失配和上/下电流的馈通到电压输出。 可以通过使用基于电荷泵中的直流参考电压的差分开关（M 1和M 2，以及M 3和M 4）来消除输入信号的馈通，并且还消除了电荷泵中的上/下电流的失配 通过使用反馈应用新的副本偏移来实现宽电压输出范围。

公开(公告)号：US07079600B2

公开(公告)日：2006-07-18

申请号：US10438297

申请日：2003-05-13

申请人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03D3/00

CPC分类号： H04L27/1563

摘要： A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

摘要翻译： 公开了一种用于提供使用DLL的FSK解调器和解调方法的系统和方法，该解调方法检测与两个调制频率对应的方波的上升沿的时间顺序和中间频率，并将相关频率解调为数据。 FSK解调器包括带通滤波器，用于转换滤波成方波的频率的波形的限幅器，用于从幅度限制器接收方波并延迟方波延迟时间的延迟线，延迟 用于接收来自幅度限制器的输出信号和来自延迟线的输出信号的触发器（DFF），在给定时间确定两个输入信号的哪个上升沿较早，并将该确定结果作为数据输出， 以及锁定延迟线的延迟时间的DLL电路。

公开(公告)号：US06501336B2

公开(公告)日：2002-12-31

申请号：US09761688

申请日：2001-01-18

申请人： Beomsup Kim ,  Chan-Hong Park

发明人： Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L7089

CPC分类号： H03L7/0893 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/1974 ,  H03L2207/06

摘要： Disclosed is a self-calibration device for calibrating a phase difference between output waveforms of a ring oscillator, comprising: a voltage-controlled oscillator adapted to adjust the transition time of an output signal according to an inputting of a control voltage for controlling the phase offset and generate the adjusted output signal; a divider adapted to divide a frequency of the output signal generated from the voltage-controlled oscillator by a fractional number to generate a plurality of output waveforms having different phases with them having an identical phase difference each other; a phase-locked loop (PLL) circuit adapted to correctly make a frequency and phase of the output signal of the divider coincident with those of a system clock, the phase-locked loop (PLL) circuit including at least a phase-frequency detecting means adapted to compare the frequency and phase of the output signal with those of the system clock and to output a result of the comparison; and a phase offset calibrating loop circuit adapted to generate a control voltage for detecting a phase offset between output waveforms of the voltage-controlled oscillator and controlling the detected phase offset according to the result of the comparison inputted thereto from the phase-frequency detecting means for application to the voltage-controlled oscillator.

摘要翻译： 公开了一种用于校准环形振荡器的输出波形之间的相位差的自校准装置，包括：压控振荡器，其适于根据用于控制相位偏移的控制电压的输入来调整输出信号的转换时间 并产生调整后的输出信号; 分频器，用于将从压控振荡器产生的输出信号的频率除以分数，以产生具有不同相位的多个输出波形，它们彼此具有相同的相位差; 锁相环（PLL）电路，其适于正确地使分频器的输出信号的频率和相位与系统时钟的输出信号的频率和相位一致，所述锁相环（PLL）电路至少包括相位频率检测装置 适于将输出信号的频率和相位与系统时钟的频率和相位进行比较，并输出比较结果; 以及相位偏移校准环路电路，其适于产生用于检测压控振荡器的输出波形之间的相位偏移的控制电压，并且根据从相位频率检测装置输入的比较结果来控制检测到的相位偏移， 应用于压控振荡器。