公开(公告)号：US20010012999A1

公开(公告)日：2001-08-09

申请号：US09795070

申请日：2001-02-26

申请人： Compaq Computer Corp.,

发明人： Anthony J. Vitale ,  Ginger Chun-Che Lin ,  Thomas Kopec

IPC分类号： G10L013/00

CPC分类号： G10L13/08

摘要： A computerized apparatus for reducing the size of a dictionary used in a text-to-speech synthesis system are provided. In an initial phase, the method and apparatus determine if entries in the dictionary, each containing a grapheme string and a corresponding phoneme string, can be fully matched by using at least one rule set used to synthesize words to phonemic data. If the entry can be fully matched using rule processing alone, the entry is indicated to be deleted from the dictionary. In a second phase, the method and apparatus determine if the entry, considered as a root word entry, is required in the dictionary in order to support phoneme synthesis of other entries containing the root word entry, and if so, the root word entry is indicated to be saved in the dictionary. If the other entries containing the root word entry can have correct phonemic data generated from a combination of the root word entries phonemic data and phonemes generated from rule set processing, then the other entries are indicated to be deleted from the dictionary. After all words have been processed by phase one and/or phase two, the entries indicated to be saved are aggregated to form a reduced dictionary.

摘要翻译： 提供了一种用于减小文本到语音合成系统中使用的字典大小的计算机化装置。 在初始阶段，方法和装置通过使用至少一个用于将单词合成到音素数据的规则集来确定字典中每个包含字母串和对应音素串的条目是否可以完全匹配。 如果条目可以单独使用规则处理完全匹配，则表示该条目从字典中删除。 在第二阶段中，方法和装置确定在词典中是否需要被视为根词条目的条目，以支持包含根词条目的其他条目的音素合成，如果是，则根词条目是 表示保存在字典中。 如果包含根词条目的其他条目可以具有从根词条目音素数据和从规则集处理生成的音素的组合产生的正确音素数据，则其他条目被指示为从字典中删除。 在所有单词已被第一阶段和/或第二阶段处理之后，表示要保存的条目被聚合以形成缩减的字典。

公开(公告)号：US6122714A

公开(公告)日：2000-09-19

申请号：US957298

申请日：1997-10-24

申请人： Stephen R. VanDoren ,  Simon C. Steely ,  Madhumitra Sharma ,  David M. Fenwick

发明人： Stephen R. VanDoren ,  Simon C. Steely ,  Madhumitra Sharma ,  David M. Fenwick

IPC分类号： G06F12/08 ,  G06F9/46 ,  G06F15/167 ,  G06F12/16

CPC分类号： G06F9/52

摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.

摘要翻译： 用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。 在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。 存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。 每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。 受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。 通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。 耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。 消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。 因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。 使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

公开(公告)号：US6108741A

公开(公告)日：2000-08-22

申请号：US655254

申请日：1996-06-05

申请人： John M. MacLaren ,  Alan L. Goodrum

发明人： John M. MacLaren ,  Alan L. Goodrum

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/38

CPC分类号： G06F13/4036

摘要： A computer system includes a first device on a first data bus, a second device on a second data bus, and a bridge device that delivers data transactions between the two devices. The bridge device includes an execution queue that stores only a higher priority transaction and transactions initiated before the higher priority transaction, and a controller that selects transactions from the execution queue to be completed on one of the data buses.

摘要翻译： 计算机系统包括第一数据总线上的第一设备，第二数据总线上的第二设备以及在两个设备之间传送数据事务的桥接设备。 桥接设备包括仅存储较高优先级事务的执行队列和在较高优先级事务之前发起的事务，以及从执行队列中选择要在其中一条数据总线上完成的事务的控制器。

公开(公告)号：US6105146A

公开(公告)日：2000-08-15

申请号：US226359

申请日：1999-01-06

申请人： Siamak Tavallaei ,  Louis R. Gagliardi ,  Joseph Peter Miller

发明人： Siamak Tavallaei ,  Louis R. Gagliardi ,  Joseph Peter Miller

IPC分类号： G06F11/00 ,  G06F11/20

CPC分类号： G06F11/2017 ,  G06F11/0745 ,  G06F11/0751

摘要： A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.

摘要翻译： 用于主机服务器系统的系统管理模块（SMM）包括连接到系统管理本地总线的系统管理处理器（SMP）。 系统管理本地总线通过系统管理中心（SMC）连接到系统PCI总线。 SMC包括PCI总线的主要仲裁单元，还包括系统管理本地总线的仲裁器。 SMM包括连接到系统管理本地总线的视频控制器和键盘和鼠标控制器，以支持SMM的远程安装。 SMC包括监视PCI周期的逻辑，并在发生系统错误时发出错误信号。 SMC还通过屏蔽失败设备的请求，授权和中断线来隔离故障组件。 此外，如果提供备用组件，则SMC允许动态切换到备用组件。 除了检测错误和执行生存和维护操作之外，SMC通过支持主目标优先级确定来提高系统性能，从而更有效地仲裁系统总线（如PCI总线）的掌握。

公开(公告)号：US6098134A

公开(公告)日：2000-08-01

申请号：US775130

申请日：1996-12-31

申请人： Peter Michels ,  Christopher J. Pettey ,  Thomas R. Seeman ,  Brian S. Hausauer

发明人： Peter Michels ,  Christopher J. Pettey ,  Thomas R. Seeman ,  Brian S. Hausauer

IPC分类号： G06F9/46 ,  G06F13/38 ,  G06F15/17

CPC分类号： G06F9/52

摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus. Split transactions are done by a "retry" command on a PCI bus, wherein a read request that cannot be completed immediately is queued and a "retry" response is sent back to the requester on the bus; this instructs the requester to retry (send the same command again) at a later time. To avoid a situation where two processors issue locked cycles which are enqueued and retried in separate bridges, a "Superlock" signal is added to the processor bus, which is asserted by a bridge as soon as a locked transaction is enqueued, and thereafter neither bridge will accept a locked cycle issued by a processor, other than that locked read that was initiated by a processor and enqueued in the bridge and is being retried.

摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI至（E）ISA网桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 根据本发明的特征，提供分割事务，即，在请求它的处理器仍然在总线上时不满足的读请求，而是在读取结果为止之前放弃总线并且其他事务干预 可用。 诸如P6的当代微处理器具有延迟事务协议来实现分离事务，但是该协议在PCI总线上不可用。 拆分事务通过PCI总线上的“重试”命令完成，其中立即不能完成的读取请求被排队，并且“重试”响应被发送回总线上的请求者; 这指示请求者稍后重试（再次发送相同的命令）。 为了避免两个处理器发出锁定循环的情况，这些循环在单独的桥接器中排队并重试，“Superlock”信号被添加到处理器总线中，一旦锁定的事务被入队就由桥接器断言，然后两个桥接器 将接受处理器发出的锁定循环，而不是由处理器启动并处于桥中并正在重试的锁定读取。

公开(公告)号：US6061521A

公开(公告)日：2000-05-09

申请号：US759042

申请日：1996-12-02

申请人： John S. Thayer ,  Gary W. Thome ,  John G. Favor ,  Frederick D. Weber

发明人： John S. Thayer ,  Gary W. Thome ,  John G. Favor ,  Frederick D. Weber

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3824

摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers may be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, an arithmetic logic unit may be partitioned into at least two logic portions. A first logic portion may be coupled to receive a first operand from a fixed slot of a first register and a second operand from any slot of a second register. A second logic portion may be coupled to receive a third operand from a fixed slot of the first register and a fourth operand from any slot of the second register. The first logic portion may perform an arithmetic operation dissimilar from the second logic portion.

摘要翻译： 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地路由和组合在矢量ALU。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。 在一个实施例中，算术逻辑单元可以被划分为至少两个逻辑部分。 第一逻辑部分可以被耦合以从第二寄存器的任何时隙的第一寄存器的固定时隙和第二操作数接收第一操作数。 第二逻辑部分可以被耦合以从第一寄存器的固定时隙接收第三操作数，并从第二寄存器的任何时隙接收第四操作数。 第一逻辑部分可以执行与第二逻辑部分不同的算术运算。

公开(公告)号：US06047372A

公开(公告)日：2000-04-04

申请号：US290837

申请日：1999-04-13

申请人： John S. Thayer ,  Brian E. Longhenry ,  John G. Favor ,  Frederick D. Weber

发明人： John S. Thayer ,  Brian E. Longhenry ,  John G. Favor ,  Frederick D. Weber

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F7/00

CPC分类号： G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3877

摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment multiple ALUs may each receive one operand from a fixed source register slot location, where the fixed slot location may be different for each ALU. The operand routing may provide another operand from any source register slot location for another input to each respective ALU.

摘要翻译： 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。 在一个实施例中，多个ALU可以从固定的源寄存器时隙位置接收一个操作数，其中固定的时隙位置对于每个ALU可以是不同的。 操作数路由可以从任何源寄存器时隙位置提供另一个操作数，用于另一个输入到每个相应的ALU。

公开(公告)号：US6035362A

公开(公告)日：2000-03-07

申请号：US658728

申请日：1996-06-05

申请人： Alan L. Goodrum ,  John M. MacLaren ,  Paul R. Culley

发明人： Alan L. Goodrum ,  John M. MacLaren ,  Paul R. Culley

IPC分类号： G06F13/36 ,  G06F12/08 ,  G06F13/40

CPC分类号： G06F13/4059

摘要： A computer system includes a first device on the first data bus, a second device on the second data bus, and a bridge device that delivers requests for data from the first device to the second device and returns the requested data to the first device. The bridge device includes a first data storage buffer that stores data requested by the first device during the first request, and a second data buffer that simultaneously stores data requested by the first device during a second request.

摘要翻译： 计算机系统包括第一数据总线上的第一设备，第二数据总线上的第二设备以及将数据从第一设备传送到第二设备并将所请求的数据返回到第一设备的桥接设备。 桥接器件包括第一数据存储缓冲器，其存储在第一请求期间由第一器件请求的数据，以及第二数据缓冲器，其在第二请求期间同时存储由第一器件请求的数据。

公开(公告)号：US5991830A

公开(公告)日：1999-11-23

申请号：US885144

申请日：1997-06-30

申请人： Paul F. Beard ,  Mark D. Moore

发明人： Paul F. Beard ,  Mark D. Moore

IPC分类号： G06F12/06 ,  G06F13/00

CPC分类号： G06F12/0676 ,  G06F12/0684

摘要： A system for allowing a peripheral device to be inserted directly into a port of a computer system while the computer system is powered on. The insertion of a peripheral device into the computer system port is automatically detected, and a configuration operation is automatically performed when insertion of the peripheral device is detected. The system also allows a plurality of peripheral devices to be connected to a single port of a computer system by automatically determining the number of peripheral devices and assigning a unique address to each of the peripheral devices. The peripheral device may have a host port for communicating with the computer system, a slave port for connecting to a slave device, and a device manager which identifies if a slave device is connected.

摘要翻译： 一种用于在计算机系统通电时允许外围设备直接插入计算机系统的端口的系统。 自动检测外围设备插入计算机系统端口，并且当检测到外围设备的插入时，自动执行配置操作。 该系统还允许多个外围设备通过自动确定外围设备的数量并向每个外围设备分配唯一的地址而连接到计算机系统的单个端口。 外围设备可以具有用于与计算机系统进行通信的主机端口，用于连接到从设备的从端口以及用于识别从设备是否连接的设备管理器。

公开(公告)号：US5914727A

公开(公告)日：1999-06-22

申请号：US925773

申请日：1997-09-09

申请人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

发明人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

IPC分类号： G06F12/02 ,  G06F12/10 ,  H04N7/26 ,  H04N7/50 ,  G06F15/16

CPC分类号： G06F12/1081 ,  G06F12/0292 ,  H04N19/423 ,  H04N19/61

摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST. An AGP Valid bit is set to indicate whether an AGP device is present or not. If the AGP device is not present, then no virtual memory address space is allocated during the computer system startup.

摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 必须为计算机系统的可寻址存储空间内的AGP设备分配连续的虚拟内存地址空间，通常使用32位寻址4 GB。 从AGP设备确定AGP所需的虚拟内存地址空间量，并将信息放入核心逻辑的寄存器，以便计算机系统软件可以在计算机系统中分配所需量的存储器并分配基地址 启动或POST。 AGP有效位设置为指示AGP设备是否存在。 如果AGP设备不存在，则在计算机系统启动期间不会分配虚拟内存地址空间。