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公开(公告)号：US20110116806A1
公开(公告)日：2011-05-19
申请号：US12618735
申请日：2009-11-15
申请人： Runsheng HE
发明人： Runsheng HE
CPC分类号： H04L25/03019 , H04L25/03057
摘要： A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design that operates at frequencies above 10 GHz, making it feasible to employ decision feedback equalization in optical transceiver modules. An adaptation technique is also disclosed to maximize communications reliability. The adaptation module can be treated as a straightforward extension of the pre-computation unit. At least some method embodiments include, in each time interval: sampling a signal that is partially compensated by a feedback signal; comparing the sampled signal to a set of thresholds to determine multiple speculative decisions; selecting and outputting one of the speculative decisions based on preceding decisions; and updating a counter if the sampled signal falls within a window proximate to a given threshold. Once a predetermined interval has elapsed, the value accumulated by the counter is used to adjust the given threshold.
摘要翻译： 当采用并行化和预计算技术时，判决反馈均衡器（DFE）可以以更高的频率运行。 这里公开的是在10GHz以上的频率工作的DFE设计，使得在光收发模块中采用判决反馈均衡是可行的。 还公开了适应技术以最大化通信可靠性。 适配模块可以被视为预计算单元的直接扩展。 至少一些方法实施例在每个时间间隔中包括：对由反馈信号部分补偿的信号进行采样; 将采样信号与一组阈值进行比较以确定多个推测性决策; 基于以前的决策选择和输出其中一个投机决策; 以及如果采样信号落在靠近给定阈值的窗口内，则更新计数器。 一旦经过预定间隔，则由计数器累积的值用于调整给定的阈值。
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公开(公告)号：US20110069791A1
公开(公告)日：2011-03-24
申请号：US12565817
申请日：2009-09-24
申请人： Runsheng HE
发明人： Runsheng HE
IPC分类号： H04L27/06
CPC分类号： H04L25/03178 , H03M13/3723 , H03M13/3972 , H03M13/41 , H03M13/6561 , H04L1/0054 , H04L25/03331 , H04L25/14
摘要： A parallel implementation of the Viterbi decoder becomes more efficient when it employs end-state information passing as disclosed herein. The improved efficiency enables the usage of less area and/or provides the capacity to handle higher data rates within a given heat budget. In at least some embodiments, a decoder chip employs multiple decoders that operate in parallel on a stream of overlapping data blocks, using add-compare-select operations, to obtain a sequence of state metrics representing a most likely path to each state. Each decoder passes information indicative of a selected end-state for a decoder operating on a preceding data block. Each decoder in turn receives, from a decoder operating on a subsequent data block, the information indicative of the selected end-state. The end-state information eliminates any need for post-data processing, thereby abbreviating the decoding process.
摘要翻译： 当维特比解码器采用如本文所公开的终端状态信息传递时，并行实现变得更有效。 提高的效率使得能够使用更少的面积和/或提供在给定的热预算内处理更高数据速率的能力。 在至少一些实施例中，解码器芯片使用多个解码器，其使用加法比较选择操作在重叠数据块的流上并行操作，以获得表示每个状态的最可能路径的状态度量序列。 每个解码器传递指示在前一数据块上操作的解码器的所选择的结束状态的信息。 每个解码器又从在后续数据块上操作的解码器接收指示所选择的结束状态的信息。 结束状态信息消除了对数据后处理的任何需要，从而缩短了解码过程。
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公开(公告)号：US20140056346A1
公开(公告)日：2014-02-27
申请号：US13594595
申请日：2012-08-24
申请人： Haoli QIAN , Yat-tung LAM , Runsheng HE
发明人： Haoli QIAN , Yat-tung LAM , Runsheng HE
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04B10/6971 , H04L2025/03356 , H04L2025/03496
摘要： A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules. One illustrative embodiment includes a front end filter to reduce leading intersymbol interference in a receive signal; a serial-to-parallel converter and at least one pre-compensation unit that together convert the filtered signal into grouped sets of tentative decisions, the sets in each group being made available in parallel; a set of pipelined DFE multiplexer units to select a contingent symbol decision from each set of tentative decisions to form groups of contingent symbol decisions based on a presumed sequence of preceding symbol decisions; and an output multiplexer that chooses, based on preceding symbol decisions, one of said groups of contingent symbol decisions.
摘要翻译： 当采用并行化和预计算技术时，判决反馈均衡器（DFE）可以以更高的频率运行。 这里公开了一种DFE设计，其适用于均衡接收信号，比特率高于10GHz，使得在硅基光收发器模块中采用判决反馈均衡是可行的。 一个说明性实施例包括前端滤波器以减少接收信号中的前导符号间干扰; 串行到并行转换器和至少一个预补偿单元，其将滤波的信号一起转换成分组的一组暂定决定，每组中的组并行可用; 一组流水线DFE多路复用器单元，用于从每组暂定决定中选择或有符号决定，以基于先前符号决定的推定序列形成组合的偶然符号决定; 以及输出多路复用器，其基于先前的符号判定来选择所述组的偶然符号决定中的一个。
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公开(公告)号：US08427353B2
公开(公告)日：2013-04-23
申请号：US13027625
申请日：2011-02-15
IPC分类号： H03M1/36
摘要： Disclosed is at least one flash analog-to-digital converter embodiment having a linear voltage ladder, a set of comparators each of which is coupled to one or more operational amplifiers by a sampling switch. Each of the sampling switches samples the comparator output, using the parasitic capacitance of the operational amplifier to hold the voltage. The sampling switches may be single transistors. Some embodiments further include, for each comparator, multiple operational amplifiers each of which drives a binary latch via a gating switch. The gating switches operate in sequence to distribute sequential samples to different latches. At least some embodiments of the flash converter further include an automatic gain control (AGC) that has both differential input terminals and differential output terminals. In such embodiments the comparators compare the differential output of the AGC to a differential reference voltage, and may further provide the result as a differential signal.
摘要翻译： 公开了具有线性电压梯度的至少一个闪存模数转换器实施例，一组比较器，每个比较器通过采样开关耦合到一个或多个运算放大器。 每个采样开关对比较器输出进行采样，使用运算放大器的寄生电容来保持电压。 采样开关可以是单个晶体管。 一些实施例还包括每个比较器多个运算放大器，每个运算放大器经由门控开关驱动二进制锁存器。 门控开关按顺序操作，以将顺序样本分配到不同的锁存器。 闪存转换器的至少一些实施例还包括具有差分输入端和差分输出端两者的自动增益控制（AGC）。 在这样的实施例中，比较器将AGC的差分输出与差分参考电压进行比较，并且还可以将结果作为差分信号提供。
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公开(公告)号：US20120207247A1
公开(公告)日：2012-08-16
申请号：US13027625
申请日：2011-02-15
摘要： Disclosed is at least one flash analog-to-digital converter embodiment having a linear voltage ladder, a set of comparators each of which is coupled to one or more operational amplifiers by a sampling switch. Each of the sampling switches samples the comparator output, using the parasitic capacitance of the operational amplifier to hold the voltage. The sampling switches may be single transistors. Some embodiments further include, for each comparator, multiple operational amplifiers each of which drives a binary latch via a gating switch. The gating switches operate in sequence to distribute sequential samples to different latches. At least some embodiments of the flash converter further include an automatic gain control (AGC) that has both differential input terminals and differential output terminals. In such embodiments the comparators compare the differential output of the AGC to a differential reference voltage, and may further provide the result as a differential signal.
摘要翻译： 公开了具有线性电压梯度的至少一个闪存模数转换器实施例，一组比较器，每个比较器通过采样开关耦合到一个或多个运算放大器。 每个采样开关对比较器输出进行采样，使用运算放大器的寄生电容来保持电压。 采样开关可以是单个晶体管。 一些实施例还包括每个比较器多个运算放大器，每个运算放大器经由门控开关驱动二进制锁存器。 门控开关按顺序操作，以将顺序样本分配到不同的锁存器。 闪存转换器的至少一些实施例还包括具有差分输入端和差分输出端两者的自动增益控制（AGC）。 在这样的实施例中，比较器将AGC的差分输出与差分参考电压进行比较，并且还可以将结果作为差分信号提供。
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公开(公告)号：US09071479B2
公开(公告)日：2015-06-30
申请号：US13594595
申请日：2012-08-24
申请人： Haoli Qian , Yat-tung Lam , Runsheng He
发明人： Haoli Qian , Yat-tung Lam , Runsheng He
CPC分类号： H04L25/03057 , H04B10/6971 , H04L2025/03356 , H04L2025/03496
摘要： A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules. One illustrative embodiment includes a front end filter to reduce leading intersymbol interference in a receive signal; a serial-to-parallel converter and at least one pre-compensation unit that together convert the filtered signal into grouped sets of tentative decisions, the sets in each group being made available in parallel; a set of pipelined DFE multiplexer units to select a contingent symbol decision from each set of tentative decisions to form groups of contingent symbol decisions based on a presumed sequence of preceding symbol decisions; and an output multiplexer that chooses, based on preceding symbol decisions, one of said groups of contingent symbol decisions.
摘要翻译： 当采用并行化和预计算技术时，判决反馈均衡器（DFE）可以以更高的频率运行。 这里公开了一种DFE设计，其适用于均衡接收信号，比特率高于10GHz，使得在硅基光收发器模块中采用判决反馈均衡是可行的。 一个说明性实施例包括前端滤波器以减少接收信号中的前导符号间干扰; 串行到并行转换器和至少一个预补偿单元，其将滤波的信号一起转换成分组的一组暂定决定，每组中的组并行可用; 一组流水线DFE多路复用器单元，用于从每组暂定决定中选择或有符号决定，以基于先前符号决定的推定序列形成组合的偶然符号决定; 以及输出多路复用器，其基于先前的符号判定来选择所述组的偶然符号决定中的一个。
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公开(公告)号：US08638886B2
公开(公告)日：2014-01-28
申请号：US12565817
申请日：2009-09-24
申请人： Runsheng He
发明人： Runsheng He
CPC分类号： H04L25/03178 , H03M13/3723 , H03M13/3972 , H03M13/41 , H03M13/6561 , H04L1/0054 , H04L25/03331 , H04L25/14
摘要： A parallel implementation of the Viterbi decoder becomes more efficient when it employs end-state information passing as disclosed herein. The improved efficiency enables the usage of less area and/or provides the capacity to handle higher data rates within a given heat budget. In at least some embodiments, a decoder chip employs multiple decoders that operate in parallel on a stream of overlapping data blocks, using add-compare-select operations, to obtain a sequence of state metrics representing a most likely path to each state. Each decoder passes information indicative of a selected end-state for a decoder operating on a preceding data block. Each decoder in turn receives, from a decoder operating on a subsequent data block, the information indicative of the selected end-state. The end-state information eliminates any need for post-data processing, thereby abbreviating the decoding process.
摘要翻译： 当维特比解码器采用如本文所公开的终端状态信息传递时，并行实现变得更有效。 提高的效率使得能够使用更少的面积和/或提供在给定的热预算内处理更高数据速率的能力。 在至少一些实施例中，解码器芯片使用多个解码器，其使用加法比较选择操作在重叠数据块的流上并行操作，以获得表示每个状态的最可能路径的状态度量序列。 每个解码器传递指示在前一数据块上操作的解码器的所选择的结束状态的信息。 每个解码器又从在后续数据块上操作的解码器接收指示所选择的结束状态的信息。 结束状态信息消除了对数据后处理的任何需要，从而缩短了解码过程。
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公开(公告)号：US08301036B2
公开(公告)日：2012-10-30
申请号：US12618735
申请日：2009-11-15
申请人： Runsheng He
发明人： Runsheng He
IPC分类号： H04B10/06
CPC分类号： H04L25/03019 , H04L25/03057
摘要： A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design that operates at frequencies above 10 GHz, making it feasible to employ decision feedback equalization in optical transceiver modules. An adaptation technique is also disclosed to maximize communications reliability. The adaptation module can be treated as a straightforward extension of the pre-computation unit. At least some method embodiments include, in each time interval: sampling a signal that is partially compensated by a feedback signal; comparing the sampled signal to a set of thresholds to determine multiple speculative decisions; selecting and outputting one of the speculative decisions based on preceding decisions; and updating a counter if the sampled signal falls within a window proximate to a given threshold. Once a predetermined interval has elapsed, the value accumulated by the counter is used to adjust the given threshold.
摘要翻译： 当采用并行化和预计算技术时，判决反馈均衡器（DFE）可以以更高的频率运行。 这里公开的是在10GHz以上的频率工作的DFE设计，使得在光收发模块中采用判决反馈均衡是可行的。 还公开了适应技术以最大化通信可靠性。 适配模块可以被视为预计算单元的直接扩展。 至少一些方法实施例包括在每个时间间隔中：对由反馈信号部分补偿的信号进行采样; 将采样信号与一组阈值进行比较以确定多个推测性决策; 基于以前的决策选择和输出其中一个投机决策; 以及如果采样信号落在靠近给定阈值的窗口内，则更新计数器。 一旦经过预定间隔，则由计数器累积的值用于调整给定的阈值。
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