Systems and methods for high-throughput computations in a deep neural network

    公开(公告)号:US11341400B1

    公开(公告)日:2022-05-24

    申请号:US16117991

    申请日:2018-08-30

    发明人: Ruwan Ratnayake

    IPC分类号: G06N3/063 G06F17/16 G06N3/04

    摘要: This disclosure describes methods and systems for high-throughput computations in a fully-connected deep neural network. Specifically, a hardware-based deep neural network architecture including a set of parallel node processors is used to process node value transition between layers of the deep neural network, which usually involves a large-scale matrix multiplication. The set of parallel node processors are configured to decompose the large-scale matrix multiplication into sub-matrix multiplications with smaller sizes and thus reducing the hardware-complexity and making feasible direct implementation in hardware. With this implementation deep neural network may achieve a very high throughput and can handle a large number of processing layers.

    Media access control for frequency division full duplex in WLAN

    公开(公告)号:US11296840B1

    公开(公告)日:2022-04-05

    申请号:US16670934

    申请日:2019-10-31

    摘要: A first communication device in a wireless local area network (WLAN) determines one or more frequency division, full duplex (FDFD) parameters for an FDFD operation that includes FDFD communications via a first frequency segment and a second frequency segment. The first frequency segment and the second frequency segment are separated by a gap in frequency. The one or more FDFD parameters include a parameter indicating a duration of the FDFD operation. The first communication device generates a communication frame that includes one or more indications of the one or more FDFD parameters. The one or more indications in the communication frame include an indication of the duration of the FDFD operation. The first communication device transmits the communication frame to prompt a plurality of second communication devices to participate in the FDFD operation.

    Out of order placement of data in network devices

    公开(公告)号:US11252109B1

    公开(公告)日:2022-02-15

    申请号:US16577545

    申请日:2019-09-20

    IPC分类号: H04L12/861 H04L29/06

    摘要: A network device receives an out of order transport packet encapsulating a protocol data unit (PDU) associated with a data stream, the PDU having a PDU header that is aligned with a beginning of a payload of the transport packet. The network device locates the PDU header disposed at the beginning of the payload of the transport packet, and verifies, using information in a header digest field of the PDU, validity of the PDU header. In response to verifying validity of the PDU header, the network device identifies, based on memory placement information included in the PDU header, a memory location for placing the data in a set of memory locations, in a memory, for storing data associated with the data stream. The network device then stores the first data beginning at the identified first memory location in the set of memory locations in the memory.

    Data transfer interface with reduced signaling

    公开(公告)号:US11102680B1

    公开(公告)日:2021-08-24

    申请号:US16427573

    申请日:2019-05-31

    摘要: A wireless data transceiver includes a media access controller (MAC) that receives an inbound packet from an air interface and to buffer that packet for transport to a host, and receives an outbound packet and transfers that packet to the air interface. A host interface receives the inbound packet from the MAC and transfers the inbound packet to the host, and receives the outbound packet from the host for transfer to the MAC. Transport controller circuitry (TCC), including processing circuitry configured to execute instructions, manages the transceiver. Hardware data transport circuitry (HDTC) for transporting packets in either direction between the MAC and the host interface includes a buffer memory having a plurality of slots. The TCC or HDTC issues a start or stop signal to the host interface causing the HDTC and the host interface to begin or end transfer of data between the buffer memory and the host interface.

    ELIMINATING EXECUTION OF INSTRUCTIONS THAT PRODUCE A CONSTANT RESULT

    公开(公告)号:US20210165654A1

    公开(公告)日:2021-06-03

    申请号:US16702446

    申请日:2019-12-03

    发明人: David CARLSON

    IPC分类号: G06F9/30 G06F9/38

    摘要: An instruction is received by a processing pipeline of a computer processor. The instruction is a constant-type of instruction and has an associated constant value. A constant register file is assigned to the instruction. The constant value is written to the constant register file without sending the instruction to execution units (e.g., arithmetic logic units) in the processor pipeline.

    Optimized bloom filter
    9.
    发明授权

    公开(公告)号:US11005950B1

    公开(公告)日:2021-05-11

    申请号:US15040764

    申请日:2016-02-10

    发明人: Paul A. Lambert

    摘要: A method, implemented in a communication device, of indicating a service supported by the communication device. A hash value is generated, using a hash function, based on a service identifier associated with the service. Respective portions of the hash value are mapped to respective bit locations in a bit string that represents membership of the service in a set of services supported by the communication device. The bit string is generated at least by setting the bit locations in the bit string to values that indicate that the service is supported by the communication device.