公开(公告)号：US08539141B2

公开(公告)日：2013-09-17

申请号：US13197056

申请日：2011-08-03

申请人： Christophe Laurent ,  Andrea Martinelli ,  Stefan Schippers ,  Graziano Mirichigni

发明人： Christophe Laurent ,  Andrea Martinelli ,  Stefan Schippers ,  Graziano Mirichigni

IPC分类号： G06F12/00

CPC分类号： G11C16/06

摘要： A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.

摘要翻译： 一种用于访问非易失性存储器件的方法，所述非易失性存储器件包括至少一个存储器单元组或扇区，所述存储器单元被划分为具有两个不同数据存储密度可编程的区域，并且可通过至少两个读取模式（例如两级模式和多级模式）访问。 存储器区域被组织成包括用于存储以多级模式存储的数据的纠错码的存储器单元的子组的页面。 该方法包括在每个页面的开始处提供至少一个第一小区，其中将存储与整个页面的ECC保护有关的信息。 在小区的子组中，提供了旨在存储与同一页面的编程或擦除状态有关的信息的至少一个第二单元。 在编程中访问存储器区域的对应页面之前，读取第一和第二单元的内容。

公开(公告)号：US6069504A

公开(公告)日：2000-05-30

申请号：US146473

申请日：1998-09-03

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  H03K17/16 ,  H03K5/00

CPC分类号： H03K17/164 ,  G11C7/1051

摘要： An output driver circuit offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry is described for improving high frequency operation.

摘要翻译： 输出驱动器电路为同步存储器（例如同步动态随机存取存储器（SDRAM））中的高速数据通信提供控制和逻辑电平调整。 电平调节通过端接电阻之间的电阻分压和输出节点与VDD和VSS电源之间的可控阻抗获得。 响应于输入信号的转变，控制功能包括输出节点处信号的转换速率修改，顺序地导通或关闭输出晶体管。 输出晶体管的不同加权方案获得输出信号的不同特性。 描述负载匹配电路和电压电平强制电路以改善高频操作。

公开(公告)号：US10685718B2

公开(公告)日：2020-06-16

申请号：US16173557

申请日：2018-10-29

申请人： Micron Technnology, Inc.

发明人： David Aaron Palmer

IPC分类号： G11C16/26 ,  G11C16/32 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

摘要： Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.