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公开(公告)号：US08015345B2
公开(公告)日：2011-09-06
申请号：US11787101
申请日：2007-04-13
IPC分类号： G06F12/00
CPC分类号： G11C16/06
摘要： A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.
摘要翻译： 一种用于访问非易失性存储器件的方法，所述非易失性存储器件包括至少一个存储器单元组或扇区，所述存储器单元被划分为具有两个不同数据存储密度可编程的区域，并且可通过至少两个读取模式（例如两级模式和多级模式）访问。 存储器区域被组织成包括用于存储以多级模式存储的数据的纠错码的存储器单元的子组的页面。 该方法包括在每个页面的开始处提供至少一个第一小区，其中将存储与整个页面的ECC保护有关的信息。 在小区的子组中，提供了旨在存储与同一页面的编程或擦除状态有关的信息的至少一个第二单元。 在编程中访问存储器区域的对应页面之前，读取第一和第二单元的内容。
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公开(公告)号：US08539141B2
公开(公告)日：2013-09-17
申请号：US13197056
申请日：2011-08-03
IPC分类号： G06F12/00
CPC分类号： G11C16/06
摘要： A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.
摘要翻译： 一种用于访问非易失性存储器件的方法，所述非易失性存储器件包括至少一个存储器单元组或扇区，所述存储器单元被划分为具有两个不同数据存储密度可编程的区域，并且可通过至少两个读取模式（例如两级模式和多级模式）访问。 存储器区域被组织成包括用于存储以多级模式存储的数据的纠错码的存储器单元的子组的页面。 该方法包括在每个页面的开始处提供至少一个第一小区，其中将存储与整个页面的ECC保护有关的信息。 在小区的子组中，提供了旨在存储与同一页面的编程或擦除状态有关的信息的至少一个第二单元。 在编程中访问存储器区域的对应页面之前，读取第一和第二单元的内容。
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公开(公告)号：US20110289389A1
公开(公告)日：2011-11-24
申请号：US13197056
申请日：2011-08-03
CPC分类号： G11C16/06
摘要： A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.
摘要翻译： 一种用于访问非易失性存储器件的方法，所述非易失性存储器件包括至少一个存储器单元组或扇区，所述存储器单元被划分为具有两个不同数据存储密度可编程的区域，并且可通过至少两个读取模式（例如两级模式和多级模式）访问。 存储器区域被组织成包括用于存储以多级模式存储的数据的纠错码的存储器单元的子组的页面。 该方法包括在每个页面的开始处提供至少一个第一小区，其中将存储与整个页面的ECC保护有关的信息。 在小区的子组中，提供了旨在存储与同一页面的编程或擦除状态有关的信息的至少一个第二单元。 在编程中访问存储器区域的对应页面之前，读取第一和第二单元的内容。
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公开(公告)号：US20070283082A1
公开(公告)日：2007-12-06
申请号：US11787101
申请日：2007-04-13
IPC分类号： G06F12/00
CPC分类号： G11C16/06
摘要： A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region.
摘要翻译： 一种用于访问非易失性存储器件的方法，所述非易失性存储器件包括至少一个存储器单元组或扇区，所述存储器单元被划分为具有两个不同数据存储密度可编程的区域，并且可通过至少两个读取模式（例如两级模式和多级模式）访问。 存储器区域被组织成包括用于存储以多级模式存储的数据的纠错码的存储器单元的子组的页面。 该方法包括在每个页面的开始处提供至少一个第一小区，其中将存储与整个页面的ECC保护有关的信息。 在小区的子组中，提供了旨在存储与同一页面的编程或擦除状态有关的信息的至少一个第二单元。 在编程中访问存储器区域的对应页面之前，读取第一和第二单元的内容。
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公开(公告)号：US20050013170A1
公开(公告)日：2005-01-20
申请号：US10835538
申请日：2004-04-29
摘要： A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.
摘要翻译： 提出了一种用于驱动控制非易失性存储器件的至少一个存储器单元的存储器线路的电路，该电路响应于第一和第二选择信号，每个选择信号适合于采用第一逻辑值或第二逻辑值 ，其中所述电路包括用于将所述第一选择信号转换为第一操作信号的第一电平移位器和用于将所述第二选择信号转换为第二操作信号的第二电平移位器，每个电平移位器包括用于移动所述逻辑中的一个的第一移位装置 将相应的选择信号的值转换为第一偏置电压;以及选择器，用于根据第二操作信号将第一操作信号或第二偏置电压施加到存储器线; 在本发明的电路中，每个电平移位器还包括第二移位装置，用于将相应的选择信号的另一个逻辑值移位到第二偏置电压。
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公开(公告)号：US07023738B2
公开(公告)日：2006-04-04
申请号：US10835538
申请日：2004-04-29
IPC分类号： G11C16/06
摘要： A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.
摘要翻译： 提出了一种用于驱动控制非易失性存储器件的至少一个存储器单元的存储器线路的电路，该电路响应于第一和第二选择信号，每个选择信号适合于采用第一逻辑值或第二逻辑值 ，其中所述电路包括用于将所述第一选择信号转换为第一操作信号的第一电平移位器和用于将所述第二选择信号转换为第二操作信号的第二电平移位器，每个电平移位器包括用于移动所述逻辑中的一个的第一移位装置 将相应的选择信号的值转换为第一偏置电压;以及选择器，用于根据第二操作信号将第一操作信号或第二偏置电压施加到存储器线; 在本发明的电路中，每个电平移位器还包括第二移位装置，用于将相应的选择信号的另一个逻辑值移位到第二偏置电压。
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7.发明授权Method for programming a memory device suitable to minimize floating gate coupling and memory device 有权用于编程适于最小化浮动栅极耦合和存储器件的存储器件的方法公开(公告)号：US07688633B2
公开(公告)日：2010-03-30
申请号：US11732486
申请日：2007-04-02
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5621
摘要： Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said step of first programming occurs with a ramp gate voltage having first pitch and programs said cells of said buffer with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch lower than the pitch.
摘要翻译： 一种用于编程存储器件的方法的实施例，该存储器件包括在彼此电容性分离的单元的缓冲器中分开的存储器单元的矩阵，该方法包括：首先对属于缓冲器的所述单元进行编程; 属于所述缓冲器的所述单元的第二编程; 所述第一编程的步骤是以具有第一音调的斜坡栅极电压发生的，并且对具有较高阈值分布的所述缓冲器的所述单元进行编程，并且所述第二编程步骤以斜距低于间距的斜坡栅极电压发生。
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公开(公告)号：US08607210B2
公开(公告)日：2013-12-10
申请号：US12956660
申请日：2010-11-30
IPC分类号： G06F9/45
CPC分类号： G06F12/0246 , G06F8/66
摘要： Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.
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公开(公告)号：US20120137049A1
公开(公告)日：2012-05-31
申请号：US12956660
申请日：2010-11-30
CPC分类号： G06F12/0246 , G06F8/66
摘要： Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored n a trap address register.
摘要翻译： 本文描述的示例性实施例可以包括至少部分地响应于代码获取地址和存储在陷阱地址寄存器中的地址之间的匹配而将非易失性存储器设备内的固件执行转移到一个或多个替换指令。
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10.发明申请Method for programming a memory device suitable to minimize floating gate coupling and memory device 有权用于编程适于最小化浮动栅极耦合和存储器件的存储器件的方法公开(公告)号：US20070247917A1
公开(公告)日：2007-10-25
申请号：US11732486
申请日：2007-04-02
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5621
摘要： Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said step of first programming occurs with a ramp gate voltage having first pitch and programs said cells of said buffer with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch lower than the pitch.
摘要翻译： 一种用于编程存储器件的方法的实施例，该存储器件包括在彼此电容性分离的单元的缓冲器中分开的存储器单元的矩阵，该方法包括：首先对属于缓冲器的所述单元进行编程; 属于所述缓冲器的所述单元的第二编程; 所述第一编程的步骤是以具有第一音调的斜坡栅极电压发生的，并且对具有较高阈值分布的所述缓冲器的所述单元进行编程，并且所述第二编程步骤以斜距低于间距的斜坡栅极电压发生。
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