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    WAFER-SCALE MEMORY TECHNIQUES
    1.
    发明申请
    WAFER-SCALE MEMORY TECHNIQUES 有权

    公开(公告)号：US20210240344A1

    公开(公告)日：2021-08-05

    申请号：US17162796

    申请日：2021-01-29

    申请人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

    发明人： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

    IPC分类号： G06F3/06

    摘要： Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).

    MEMORY DEVICE INTERFACE AND METHOD
    2.
    发明申请
    MEMORY DEVICE INTERFACE AND METHOD 有权

    公开(公告)号：US20210200464A1

    公开(公告)日：2021-07-01

    申请号：US17136728

    申请日：2020-12-29

    申请人： Brent Keeth

    发明人： Brent Keeth

    IPC分类号： G06F3/06

    摘要： Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE
    5.
    发明申请
    SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 有权
    基于命令信号和操作状态解码命令的系统和方法

    公开(公告)号：US20120246434A1

    公开(公告)日：2012-09-27

    申请号：US13489246

    申请日：2012-06-05

    申请人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    发明人： Jeffrey W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

    IPC分类号： G06F12/00

    CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

    256 Meg dynamic random access memory
    8.
    发明授权
    256 Meg dynamic random access memory 有权
    256 Meg动态随机存取存储器

    公开(公告)号：US07969810B2

    公开(公告)日：2011-06-28

    申请号：US12381143

    申请日：2009-03-06

    申请人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Demer ,  Ronald L Taylor ,  John S. Mullin ,  Raymond J. Beffa ,  Frank F. Ross ,  Larry D. Kinsman

    发明人： Brent Keeth ,  Layne G. Bunker ,  Scott J. Demer ,  Ronald L Taylor ,  John S. Mullin ,  Raymond J. Beffa ,  Frank F. Ross ,  Larry D. Kinsman

    IPC分类号： G11C7/00

    CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/145 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/46 ,  G11C29/787 ,  G11C2029/0407 ,  H01L27/10805 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

    摘要翻译： 一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。 感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。 在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。 提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于来自每个象限的数据，将数据输出到数据读取复用器，数据缓冲器和数据驱动器焊盘。 写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。 提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。 多个电压源提供阵列和外围电路中所需的电压。 电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。 提供上电序列电路以控制芯片的上电。 提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。 芯片上还提供电路以支持各种类型的测试模式。

    Dual edge command
    10.
    发明授权
    Dual edge command 有权
    双边命令

    公开(公告)号：US07549033B2

    公开(公告)日：2009-06-16

    申请号：US11495418

    申请日：2006-07-28

    申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

    发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

    摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

    摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。