公开(公告)号：US5185745A

公开(公告)日：1993-02-09

申请号：US523004

申请日：1990-05-14

Applicant: Peter J. Manca, Jr.

Inventor： Peter J. Manca, Jr.

IPC: G01R31/3185 ,  G06F11/273

CPC classification number: G06F11/2736 ,  G01R31/318544 ,  G01R31/318583

Abstract: A method of diagnosing memory and CPU boards by using scan rings which are composed of interconnected shift registers. A maintenance processor (MP) down-loads vector files to the scan rings. The scan rings are transparently partitioned into subsections and each subsection and individual bits are then tagged using a high level language, i.e., a scan path diagnostic language (SPDL). The user of SPDL writes a program in SPDL language addressing a portion of the scan ring. Next, the high level commands are translated into low level machine code and run on the MP. Bits are then loaded into the scan ring and subjected to a test routine. Additional commands are given to correct any errors uncovered and the bits are then reloaded through the MP to the hardware element being tested.

Abstract translation: 通过使用由互连移位寄存器组成的扫描环来诊断存储器和CPU板的方法。 维护处理器（MP）将矢量文件下载到扫描环。 扫描环被透明地划分成子部分，然后使用高级语言（即扫描路径诊断语言（SPDL））对每个子部分和各个位进行标记。 SPDL的用户以编程扫描环的一部分的SPDL语言编写程序。 接下来，高级命令被转换为低级机器代码并在MP上运行。 然后将位装载到扫描环中并进行测试程序。 给出了额外的命令来纠正未覆盖的任何错误，然后通过MP将位重新加载到要测试的硬件元件。

公开(公告)号：US5113514A

公开(公告)日：1992-05-12

申请号：US482288

申请日：1990-02-20

Applicant: David H. Albonesi ,  Brian K. Langendorf ,  John Chang ,  John G. Faase ,  Michael J. Homberg

Inventor： David H. Albonesi ,  Brian K. Langendorf ,  John Chang ,  John G. Faase ,  Michael J. Homberg

IPC: G06F12/08

CPC classification number: G06F12/0811

Abstract: The invention comprises a system bus apparatus and method for a multi-arm, multiprocessor computer system having a main memory and localized buffer cache memories at each processor. Each block of data in a cache includes tag bits which identifies the condition of the data block in relation to the corresponding data in main memory and other caches. The system bus (SYSBUS) comprises three subparts; 1) a MESSAGE/DATA bus, 2) a REQUEST/GRANT bus and 3) a BCU bus. The MESSAGE/DATA bus is coupled to every device on the system and is used for transferring messages, data and addresses. The REQUEST/GRANT bus couples between every device on an arm of the system and that arm's bus control unit (BCU). The BCU bus couples between the various BCUs. Both the MESSAGE/DATA bus and the BCU bus include ACK/NACK/HIT bits which are used when responding to messages received over the SYSBUS to inform the message-issuing device if the devices received the message and, if so, the condition of the data in relation to other caches and main memory. The protocol allows inconsistent copies of data to exist and prevents stale data from being used erroneously by monitoring the tag bits and the ACK/NACK/HIT bits. Further, under the appropriate conditions, a copy of the most recent data block may be transferred from one cache to another (with appropriate updating of tags) without updating the main memory. When a memory operation will bring about a situation where cache coherence can no longer be maintained, main memory is updated with the most recent copy of the data and the other caches are either updated or tagged as invalid.

Abstract translation: 本发明包括一种用于多臂多处理器计算机系统的系统总线装置和方法，其在每个处理器处具有主存储器和局部缓冲高速缓冲存储器。 缓存中的每个数据块包括标识位，其标识数据块相对于主存储器和其他高速缓存中的相应数据的状态。 系统总线（SYSBUS）包括三个子部分; 1）MESSAGE / DATA总线，2）REQUEST / GRANT总线和3）BCU总线。 MESSAGE / DATA总线耦合到系统上的每个设备，并用于传输消息，数据和地址。 REQUEST / GRANT总线耦合在系统的臂上的每个设备和该臂的总线控制单元（BCU）之间。 BCU总线在各种BCU之间耦合。 MESSAGE / DATA总线和BCU总线都包括响应于通过SYSBUS接收到的消息而使用的ACK / NACK / HIT位，以通知消息发送设备，如果设备接收到消息，并且如果是，则 与其他缓存和主存相关的数据。 该协议允许存在不一致的数据副本，并通过监视标签位和ACK / NACK / HIT位来防止不正确的数据被错误地使用。 此外，在适当的条件下，最新数据块的副本可以从一个缓存传送到另一个（具有适当的标签更新）而不更新主存储器。 当存储器操作将导致无法再保持高速缓存一致性的情况时，使用最新的数据副本更新主存储器，并且将其他高速缓存更新或标记为无效。

公开(公告)号：US5058000A

公开(公告)日：1991-10-15

申请号：US368159

申请日：1989-06-15

Applicant: Landon Cox ,  Wayne Kovsky ,  Marie Mastaj

Inventor： Landon Cox ,  Wayne Kovsky ,  Marie Mastaj

IPC: G06F17/30

CPC classification number: G06F17/30569 ,  Y10S707/99942

Abstract: An improved method for access to data from a remote computer and an improved method for accessing remote heterogeneous data bases. The method includes a personal computer having an application program for processing data by keyboard input that operates on a local applications data base having files with a first file structure. A remote host computer accesses data in remote files having a second file structure. A preselected keystroke of the first computer modifies the data accession program of the remote computer to reformat retrieved data in the format of the personal computer applications program before transmission back to the personal computer, so that the personal computer resident portions of the program require no information as to where the requested data is located or what the host computer file structure is.

Abstract translation: 用于从远程计算机访问数据的改进方法和用于访问远程异构数据库的改进方法。 该方法包括具有用于通过键盘输入处理数据的应用程序的个人计算机，该应用程序对具有第一文件结构的文件的本地应用数据库进行操作。 远程主机访问具有第二文件结构的远程文件中的数据。 第一台计算机的预选击键修改远程计算机的数据存取程序，然后再传送回个人计算机，以个人计算机应用程序格式重新格式化检索的数据，使程序中的个人计算机驻留部分不需要任何信息 关于请求的数据所在的位置或主机计算机文件结构的位置。

公开(公告)号：US5019880A

公开(公告)日：1991-05-28

申请号：US142462

申请日：1988-01-07

Applicant: Leo M. Higgins, III.

Inventor： Leo M. Higgins, III.

IPC: H01L23/467

CPC classification number: H01L23/467 ,  H01L2924/0002

Abstract: A heat sink apparatus for convective cooling of circuit packages or components by direct impinging fluid operation employing a housing having an inlet port and a plurality of radially fluid flow passages communicating with the inlet port with each passage also having an outlet port. A fluid deflection member is supported with the housing in line with the inlet port and is provided with a deflection surface adapted to redirect the fluid flow from the inlet port to the air flow passages.

Abstract translation: 一种散热装置，用于通过直接冲击流体操作来对流冷却电路组件或组件，所述壳体具有入口端口和与每个通道的入口连通的多个径向流体流动通道，还具有出口。 流体偏转构件由壳体与入口口一致地支撑，并且设置有适于将流体流从入口端口重定向到空气流动通道的偏转表面。

公开(公告)号：US4918693A

公开(公告)日：1990-04-17

申请号：US149595

申请日：1988-01-28

Applicant: Joseph L. Ardini, Jr. ,  Robert J. Allison, Jr.

Inventor： Joseph L. Ardini, Jr. ,  Robert J. Allison, Jr.

IPC: G06F11/22

CPC classification number: G06F11/22

Abstract: In a computer system in which addressable components are physically organized on separately-replaceable printed circuit boards each containing an array of separately addressable components, diagnostic apparatus operates in the event of a component failure to assist a technician in physically locating the circuit board which contains the failed component. Each array includes a selection circuit which responds to component addresses located in the component array on that board. In the case of a component failure, diagnostic circuitry detects the address of the faulty component and places the address on the system address bus. The diagnostic circuitry controls each array to forward the output signal from the selection circuit on the associated printed circuit board to a register which has a position associated with each printed circuit board. Since only the selection circuit in the array which contains the faulty component responds to the address of the faulty component, the diagnostic register can be examined by the diagnostic circuitry to detect the position of the faulty board.

Abstract translation: 在可寻址组件物理地组织在可单独替换的印刷电路板上的计算机系统中，每个包含独立可寻址组件的阵列，诊断装置在部件故障的情况下操作，以协助技术人员物理地定位电路板， 组件失效 每个阵列包括一个选择电路，其响应位于该板上的组件阵列中的组件地址。 在组件故障的情况下，诊断电路检测故障组件的地址，并将地址放置在系统地址总线上。 诊断电路控制每个阵列以将来自相关印刷电路板上的选择电路的输出信号转发到具有与每个印刷电路板相关联的位置的寄存器。 由于只有包含故障部件的阵列中的选择电路才能响应故障部件的地址，所以诊断寄存器可以由诊断电路检查以检测故障板的位置。

公开(公告)号：US4875186A

公开(公告)日：1989-10-17

申请号：US834751

申请日：1986-02-28

Applicant: Carl R. Blume, Jr.

Inventor： Carl R. Blume, Jr.

IPC: G06F3/14 ,  G06F13/10

CPC classification number: G06F13/105 ,  G06F3/14

Abstract: Control apparatus allows application software written for use with peripheral devices manufactured by one company to run with other peripheral devices. The apparatus intercepts device-specific control commands generated by the software and translates the commands into commands which are compatible with the peripheral connected to the system. Non-device specific commands are passed untranslated through the control apparatus to the peripheral. More specifically, registers within the control apparatus which must be programmed with parameters unique to a particular peripheral cannot be accessed by the application software while other nonspecific registers remain read and write accessible. Peripheral-specific parameters are instead changed by a secondary processor which uses special hardware to minimize interference with the main processor.

Abstract translation: 控制装置允许与一家公司制造的外围设备一起使用的应用软件与其他外围设备一起运行。 该装置截取由软件产生的特定于设备的控制命令，并将命令转换成与连接到系统的外设兼容的命令。 非设备特定的命令通过控制设备传递到外设。 更具体地说，控制装置内必须使用特定外设所特有的参数进行编程的寄存器不能由应用软件访问，而其他非特定寄存器保持读和写可访问。 外部特定参数由二次处理器改变，二次处理器使用特殊硬件来最小化与主处理器的干扰。

公开(公告)号：US4860199A

公开(公告)日：1989-08-22

申请号：US80451

申请日：1987-07-31

Applicant: Brian K. Langendorf ,  Robert F. Beckwith

Inventor： Brian K. Langendorf ,  Robert F. Beckwith

IPC: G06F9/38

CPC classification number: G06F9/3806

Abstract: A Hashing Indexer For a Branch Cache for use in a pipelined digital processor that employs macro-instructions utilizing interpretation by micro-instructions. Each of the macro-instructions has an associated address and each of the micro instructions has an associated address. The hashing indexer includes a look-ahead-fetch system including a branch cache memory coupled to the prefetch section. An indexed table of branch target addressess each of which correspond to the address of a previously fetched instruction is stored in the branch cache memory. A predetermined number of bits representing the address of the macro-instruction being fetched is hashed with a predetermined number of bits representing the address of the micro-instruction being invoked. The indexer is used to apply the hashing result as an address to the branch memory in order to read out a unique predicted branch target address that is predictive of a branch for the hashed macro-instruction bits and micro-instruction bits. The hashing indexer disperses branch cache entries throughout the branch cache memory. Therefore, by hashing macro-instruction bits with micro-instruction bits and by dispersing the branch cache entries throughout the branch cache memory, the prediction rate of the system is increased.

Abstract translation: 用于分支缓存的散列索引器，用于使用通过微指令解释的宏指令的流水线数字处理器。 每个宏指令具有相关联的地址，并且每个微指令具有相关联的地址。 散列索引器包括包括耦合到预取部分的分支高速缓冲存储器的预读取系统。 分支目标地址的索引表中的每一个对应于先前获取的指令的地址被存储在分支高速缓冲存储器中。 表示正在取出的宏指令的地址的预定数量的位以表示正被调用的微指令的地址的预定数量的比特进行散列。 索引器用于将散列结果作为地址应用于分支存储器，以便读出预测散列的宏指令位和微指令位的分支的唯一预测分支目标地址。 散列索引器将分支高速缓存条目分散在整个分支高速缓冲存储器中。 因此，通过使用微指令位对宏指令位进行散列，并通过在分支高速缓冲存储器中分散分支高速缓存条目，增加系统的预测速率。

公开(公告)号：US4860165A

公开(公告)日：1989-08-22

申请号：US187057

申请日：1988-04-27

Applicant: Edgar Cassinelli

Inventor： Edgar Cassinelli

IPC: H01L23/36 ,  H01L23/473 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01L23/473 ,  H01L23/36 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/48095 ,  H01L2924/00014 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3011

Abstract: A semiconductor chip carrier package formed of a multi-layer circuit board having mounted therein a semiconductor chip support pad. The multi-layer circuit board is comprised of separate dielectric boards defining multiple conductive run layers including a signal layer and a plurality of power layers. A pluralilty of pins supported from the circuit board extending from one side thereof and including signal pins and power pins. The power pins are disposed peripherally outside of the signal pins. Means are provided for conductively connecting leads of the semiconductor chip to corresponding conductive runs of the signal and power layers.

Abstract translation: 一种半导体芯片载体封装，其由安装有半导体芯片支撑垫的多层电路板形成。 多层电路板由限定多个导电延伸层的单独介电板组成，包括信号层和多个功率层。 从电路板支撑的多个引脚，其从其一侧延伸并且包括信号引脚和电源引脚。 电源引脚外围设置在信号引脚之外。 提供了用于将半导体芯片的导线导通地连接到信号和功率层的相应导电运行的装置。

公开(公告)号：US4821171A

公开(公告)日：1989-04-11

申请号：US233884

申请日：1988-08-15

Applicant: Carroll A. Calamari

Inventor： Carroll A. Calamari

IPC: G06F12/10

CPC classification number: G06F12/1054

Abstract: When data is subject to relocation in the physical memory of a processing system employing a virtual memory architecture, execution of programs can be greatly improved through the use of a validation code generator, which assigns a code to each virtual-to-physical address translation prior to its entry in the address translation system. Whenever a page in memory is replaced or the buffer is purged for memory management purposes, the code generator proceeds to another code and assigns this new code to subsequent entries.

Abstract translation: 当数据在采用虚拟存储器架构的处理系统的物理存储器中进行重新定位时，可以通过使用验证代码生成器来极大地改进程序的执行，确认代码生成器将代码分配给每个虚拟到物理地址转换 到其在地址翻译系统中的输入。 每当存储器中的页面被替换或缓冲器被清除以用于存储器管理目的时，代码生成器进行另一个代码并将这个新代码分配给后续的条目。

公开(公告)号：US4818979A

公开(公告)日：1989-04-04

申请号：US834756

申请日：1986-02-28

Applicant: Donald C. Manson

Inventor： Donald C. Manson

IPC: G09G5/06 ,  G09G1/16

CPC classification number: G09G5/06

Abstract: A scanning display signal generating system for a plurality of planes includes a first look up table addressed by a first set of the planes, and a second look up table addressed by a second set of planes. A logic unit receives the outputs of the tables and provides a display signal which is a selected logical combination of the outputs. A function control unit provides a control signal to the logic unit to select the desired logical combination. A large number of planes are thus displayed using small LUT memory components, providing display values in real time to the scanner. The output of one look up table may be provided as a control signal to the logic unit. In one embodiment the first look up table is addressed by text planes, and an output therefrom provides the control signal for suppressing the output of the second look up table.

Abstract translation: 用于多个平面的扫描显示信号产生系统包括由第一组平面寻址的第一查询表和由第二组平面寻址的第二查询表。 逻辑单元接收表的输出并提供作为输出的选择的逻辑组合的显示信号。 功能控制单元向逻辑单元提供控制信号以选择期望的逻辑组合。 因此，使用小型LUT存储器组件显示大量平面，为扫描仪提供实时显示值。 可以将一个查找表的输出作为控制信号提供给逻辑单元。 在一个实施例中，第一查询表由文本平面寻址，并且其输出提供用于抑制第二查询表的输出的控制信号。