公开(公告)号：US09425775B2

公开(公告)日：2016-08-23

申请号：US14481269

申请日：2014-09-09

申请人： Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

发明人： Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

IPC分类号： H03K3/289 ,  H03K3/3562 ,  H03K3/037

CPC分类号： H03K3/35625 ,  H03K3/0372

摘要： A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

摘要翻译： 数据处理系统包括用于在第一和第二电压下提供功率的第一和第二配电网络以及触发器。 第二电压小于第一电压。 触发器包括具有连接到第一配电网络的电力节点的主锁存器，数据信号输入端和以第一电压驱动的输出信号输出，以及具有与第一电源连接的电源节点的从锁存器 配电网络，耦合到主锁存器的输出的输入，由第一电压驱动的从锁存器输出信号输出，以及具有与第二电压连接的功率节点的第一锁存逆变器的反馈电路，输入 耦合到主锁存器输出端，输出端提供由第二电压驱动的输出信号。

公开(公告)号：US20160065185A1

公开(公告)日：2016-03-03

申请号：US14472809

申请日：2014-08-29

申请人： Anis M. Jarrar ,  John M. Boyer ,  Saji George ,  David R. Tipple

发明人： Anis M. Jarrar ,  John M. Boyer ,  Saji George ,  David R. Tipple

IPC分类号： H03K3/037 ,  H03K19/20 ,  G06F11/07 ,  H03K19/0175

CPC分类号： H03K3/0375 ,  G06F11/0721 ,  G06F11/0772 ,  H03K3/0372 ,  H03K19/0175 ,  H03K19/20

摘要： A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

摘要翻译： 处理系统包括在处理器核心和外围部件中的至少一个中的处理器核心，外围部件和触发器单元。 触发器单元可以包括主锁存器和耦合到主锁存器的输出的两个从锁存器。 第一从锁存器形成在半导体衬底的第一掺杂阱区上。 第二从锁存器形成在半导体衬底的第二掺杂阱区上。 比较器耦合到第一从锁存器的输出端和第二从锁存器的输出端。 比较器的输出指示存储在第一从锁存器中的状态是否与存储在第二从锁存器中的状态相同。

公开(公告)号：US08994446B2

公开(公告)日：2015-03-31

申请号：US13930657

申请日：2013-06-28

申请人： Stefano Pietri ,  Chris C. Dao ,  Anis M. Jarrar ,  Juxiang Ren

发明人： Stefano Pietri ,  Chris C. Dao ,  Anis M. Jarrar ,  Juxiang Ren

IPC分类号： H03K3/01 ,  G05F1/10

CPC分类号： G05F1/10 ,  G05F3/205

摘要： An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.

摘要翻译： 集成电路包括形成在第一阱中的第一导电类型的器件; 电压调节器，被配置为基于使用第一带隙基准发生器产生的第一参考电压向第一阱提供偏置电压; 以及监视电路，被配置为将第一阱的电压与第一电压范围的上限和下限进行比较，其中使用第二带隙基准发生器提供上限和下限， 带隙参考发生器，其中响应于确定所述第一阱的电压在所述第一电压范围之外，提供第一超出范围指示符。

公开(公告)号：US20160072484A1

公开(公告)日：2016-03-10

申请号：US14481269

申请日：2014-09-09

申请人： Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

发明人： Anis M. Jarrar ,  John M. Dalbey ,  Alexander B. Hoefler ,  Colin MacDonald

IPC分类号： H03K3/3562

CPC分类号： H03K3/35625 ,  H03K3/0372

摘要： A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

摘要翻译： 数据处理系统包括用于在第一和第二电压下提供功率的第一和第二配电网络以及触发器。 第二电压小于第一电压。 触发器包括具有连接到第一配电网络的电力节点的主锁存器，数据信号输入端和以第一电压驱动的输出信号输出，以及具有与第一电源连接的电源节点的从锁存器 配电网络，耦合到主锁存器的输出的输入，由第一电压驱动的从锁存输出信号输出，以及具有与第二电压连接的功率节点的第一锁存逆变器的反馈电路，输入 耦合到主锁存器输出端，输出端提供由第二电压驱动的输出信号。

公开(公告)号：US09264021B1

公开(公告)日：2016-02-16

申请号：US14472809

申请日：2014-08-29

申请人： Anis M. Jarrar ,  John M. Boyer ,  Saji George ,  David R. Tipple

发明人： Anis M. Jarrar ,  John M. Boyer ,  Saji George ,  David R. Tipple

IPC分类号： H03K19/003 ,  H03K3/037 ,  H03K19/0175 ,  H03K19/20 ,  G06F11/07

CPC分类号： H03K3/0375 ,  G06F11/0721 ,  G06F11/0772 ,  H03K3/0372 ,  H03K19/0175 ,  H03K19/20

摘要： A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

摘要翻译： 处理系统包括在处理器核心和外围部件中的至少一个中的处理器核心，外围部件和触发器单元。 触发器单元可以包括主锁存器和耦合到主锁存器的输出的两个从锁存器。 第一从锁存器形成在半导体衬底的第一掺杂阱区上。 第二从锁存器形成在半导体衬底的第二掺杂阱区上。 比较器耦合到第一从锁存器的输出端和第二从锁存器的输出端。 比较器的输出指示存储在第一从锁存器中的状态是否与存储在第二从锁存器中的状态相同。

公开(公告)号：US20150002215A1

公开(公告)日：2015-01-01

申请号：US13930657

申请日：2013-06-28

申请人： Stefano Pietri ,  Chris C. Dao ,  Anis M. Jarrar ,  Juxiang Ren

发明人： Stefano Pietri ,  Chris C. Dao ,  Anis M. Jarrar ,  Juxiang Ren

IPC分类号： G05F1/10

CPC分类号： G05F1/10 ,  G05F3/205

摘要： An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.

摘要翻译： 集成电路包括形成在第一阱中的第一导电类型的器件; 电压调节器，被配置为基于使用第一带隙基准发生器产生的第一参考电压向第一阱提供偏置电压; 以及监视电路，被配置为将第一阱的电压与第一电压范围的上限和下限进行比较，其中使用第二带隙基准发生器提供上限和下限， 带隙参考发生器，其中响应于确定所述第一阱的电压在所述第一电压范围之外，提供第一超出范围指示符。

公开(公告)号：US09088280B2

公开(公告)日：2015-07-21

申请号：US14067320

申请日：2013-10-30

申请人： Anis M. Jarrar ,  Stefano Pietri ,  Steven K. Watkins

发明人： Anis M. Jarrar ,  Stefano Pietri ,  Steven K. Watkins

IPC分类号： G05F3/08 ,  H03K17/16

CPC分类号： H03K17/162 ,  H03K17/14 ,  H03K2217/0018

摘要： A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

摘要翻译： 一种体偏置控制电路，包括耦合以向身体终端提供偏置电压的输出。 体偏置控制电路被配置为在偏置电压的有效变化幅度在一段时间内变化的时间段内将偏置电压从第一偏置电压改变到第二偏置电压。 对于接近源电压的第一和第二偏置电压之间的电压，有效变化率的幅度小于进一步源极电压的第一和第二偏置电压之间的偏置电压。

公开(公告)号：US08624627B1

公开(公告)日：2014-01-07

申请号：US13538200

申请日：2012-06-29

申请人： Anis M. Jarrar ,  William C. Moyer ,  Jim C. Nash

发明人： Anis M. Jarrar ,  William C. Moyer ,  Jim C. Nash

IPC分类号： H01L25/00

CPC分类号： G06F1/3287 ,  G06F1/3228 ,  Y02D10/171

摘要： The present application discloses an integrated circuit having a power controller that can manage power modes of a system when the system is in a low power mode. According to an embodiment, a power controller is built into an input/output (I/O) region of and integrated circuit die, wherein the I/O region is outside the main logic area of the die. The same supply voltage that powers the I/O region of the device can power the power controller. The power controller can operate to transition the integrated circuit die between power modes by transitioning logic modules of the integrated circuit between power states without intervention by the logic modules.

摘要翻译： 本申请公开了一种具有功率控制器的集成电路，其能够在系统处于低功率模式时管理系统的功率模式。 根据实施例，功率控制器内置在集成电路管芯的输入/输出（I / O）区域中，其中I / O区域在管芯的主逻辑区域之外。 为器件的I / O区域供电的相同电源电压可为电源控制器供电。 功率控制器可以通过在功率状态之间转换集成电路的逻辑模块而不用逻辑模块进行干预来操作以在功率模式之间转换集成电路管芯。

公开(公告)号：US20140002132A1

公开(公告)日：2014-01-02

申请号：US13538200

申请日：2012-06-29

申请人： Anis M. Jarrar ,  William C. Moyer ,  Jim C. Nash

发明人： Anis M. Jarrar ,  William C. Moyer ,  Jim C. Nash

IPC分类号： H03K19/0175

CPC分类号： G06F1/3287 ,  G06F1/3228 ,  Y02D10/171

摘要： The present application discloses an integrated circuit having a power controller that can manage power modes of a system when the system is in a low power mode. According to an embodiment, a power controller is built into an input/output (I/O) region of and integrated circuit die, wherein the I/O region is outside the main logic area of the die. The same supply voltage that powers the I/O region of the device can power the power controller. The power controller can operate to transition the integrated circuit die between power modes by transitioning logic modules of the integrated circuit between power states without intervention by the logic modules.

摘要翻译： 本申请公开了一种具有功率控制器的集成电路，其能够在系统处于低功率模式时管理系统的功率模式。 根据实施例，功率控制器内置在集成电路管芯的输入/输出（I / O）区域中，其中I / O区域在管芯的主逻辑区域之外。 为器件的I / O区域供电的相同电源电压可为电源控制器供电。 功率控制器可以通过在功率状态之间转换集成电路的逻辑模块而不用逻辑模块进行干预来操作以在功率模式之间转换集成电路管芯。

公开(公告)号：US08604853B1

公开(公告)日：2013-12-10

申请号：US13480971

申请日：2012-05-25

申请人： Anis M. Jarrar ,  Hector Sanchez

发明人： Anis M. Jarrar ,  Hector Sanchez

IPC分类号： H03K3/289

CPC分类号： H01L23/5225 ,  H01L2924/0002 ,  H03K3/013 ,  H03K3/0375 ,  H01L2924/00

摘要： An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding.

摘要翻译： 一种集成电路，包括状态保持节点，导电时钟网络屏蔽和用于在低功率状态期间保持集成电路的状态的多个状态保持装置。 状态保持节点接收在低功率状态期间保持在工作电压电平的状态保持电源电压。 导电时钟网络屏蔽与时钟信号导体一起分布并耦合到状态保持节点。 每个状态保持装置具有耦合到时钟网络屏蔽的电源电压输入，使得它在低功率状态期间保持供电。 状态保持节点可以被实现为导电迹线的最小集合。 可以提供状态保持缓冲器用于缓冲表示低功率状态的电源门控信号，其中缓冲器具有耦合到时钟网络屏蔽的电源电压输入。