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    MULTI-CHIP MODULE
    2.
    发明申请
    MULTI-CHIP MODULE 失效
    多芯片模块

    公开(公告)号：US20120127671A1

    公开(公告)日：2012-05-24

    申请号：US12951381

    申请日：2010-11-22

    申请人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

    发明人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

    IPC分类号： H05K7/00

    CPC分类号： H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01M10/425 ,  H01M10/44 ,  H01M10/48 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A multi-chip module is disclosed to include a pin frame, an electric power switch chip, and a battery protection chip. The pin frame has a chip placement region and six pins. The second pin and the fifth pin are electrically connected at the chip placement region, and the other pins are set electrically isolated from each other. A bottom surface of the electric power switch chip is electrically connected at the chip placement region, and a top surface thereof is electrically connected to the first pin and the third pin. A bottom surface of the battery protection chip is disposed at the top surface of the electric power switch chip in an electrically isolated fashion. A top surface of the battery protection chip is electrically connected to the top surface of the electric power switch chip, the first pin, the fourth pin, and the sixth pin.

    摘要翻译： 公开了一种多芯片模块，其包括引脚框架，电力开关芯片和电池保护芯片。 引脚框架有一个芯片放置区域和六个引脚。 第二引脚和第五引脚在芯片布置区域处电连接，并且另一个引脚被设置为彼此电隔离。 电源开关芯片的底表面在芯片布置区域处电连接，并且其顶表面电连接到第一引脚和第三引脚。 电池保护芯片的底表面以电隔离的方式设置在电力开关芯片的顶表面。 电池保护芯片的顶表面电连接到电力开关芯片的顶表面，第一引脚，第四引脚和第六引脚。

    PACKAGE STRUCTURE
    3.
    发明申请
    PACKAGE STRUCTURE 审中-公开
    包装结构

    公开(公告)号：US20130075882A1

    公开(公告)日：2013-03-28

    申请号：US13244410

    申请日：2011-09-24

    申请人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

    发明人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49503 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A package structure including a first leadframe, a second leadframe, a power pin, a ground pin, a first pin, several first wires, several second wires, and a package body is disclosed. The first leadframe is used for electrically coupling to the drains of a first power transistor and the second power transistor. The ground pin is electrically coupled to the first leadframe. The first pin is connected with the first leadframe through a conductive region used for increasing the amount of current which can be loaded by the first pin. The first wires are used for electrically coupling between the first leadframe and the source of the second power transistor, for reducing the internal resistance of the second power transistor. The second wires are used for electrically coupling between the ground pin and the source of the first power transistor, for reducing the internal resistance of the first power transistor.

    摘要翻译： 公开了一种包括第一引线框，第二引线框，电源引脚，接地引脚，第一引脚，多个第一布线，多个第二布线和封装体的封装结构。 第一引线框架用于电耦合到第一功率晶体管和第二功率晶体管的漏极。 接地引脚电耦合到第一引线框架。 第一引脚通过用于增加可由第一引脚加载的电流量的导电区域与第一引线框架连接。 第一导线用于第一引线框和第二功率晶体管的源之间的电耦合，用于降低第二功率晶体管的内部电阻。 第二导线用于电连接接地引脚与第一功率晶体管的源极之间，用于降低第一功率晶体管的内部电阻。

    Digital power meter apparatus and method for the same
    4.
    发明授权
    Digital power meter apparatus and method for the same 失效
    数字式功率计装置及方法相同

    公开(公告)号：US07166995B2

    公开(公告)日：2007-01-23

    申请号：US10995496

    申请日：2004-11-24

    申请人： Yi-Chou Huang ,  Kou-Yuan Yuan ,  Arthur Shaoyan Rong

    发明人： Yi-Chou Huang ,  Kou-Yuan Yuan ,  Arthur Shaoyan Rong

    IPC分类号： G01R11/32

    CPC分类号： G01R21/133

    摘要： A digital power meter apparatus and the method for the same are proposed. The input voltage signal and input current signal through dual channels are processed at a first stage to obtained a first digital signal. The first digital signal is sent to a third low-pass filter. The input voltage signal and input current signal are processed in a second-stage processing through a first low-pass filter, a second low-pass filter and a second logic operation unit to obtain a second digital signal. A third logic operation unit processes the first digital signal and a second digital signal in order to obtain a digital power signal proportion to the product of the two input signals.

    摘要翻译： 提出了一种数字功率计装置及其方法。 通过双通道的输入电压信号和输入电流信号在第一级处理以获得第一数字信号。 第一个数字信号被发送到第三个低通滤波器。 输入电压信号和输入电流信号通过第一低通滤波器，第二低通滤波器和第二逻辑运算单元进行第二级处理，以获得第二数字信号。 第三逻辑运算单元处理第一数字信号和第二数字信号，以获得与两个输入信号的乘积成比例的数字功率信号。

    PACKAGING STRUCTURE
    5.
    发明申请
    PACKAGING STRUCTURE 审中-公开
    包装结构

    公开(公告)号：US20130075880A1

    公开(公告)日：2013-03-28

    申请号：US13244344

    申请日：2011-09-24

    申请人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

    发明人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49517 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00014

    摘要： A packaging structure comprises a first leadframe, a second leadframe, two grounding pins, two first pins, a plurality of first wires, a plurality of second wires, and a package body. The second leadframe is coupled to the drains of a first power transistor and a second power transistor. The two grounding pins are adjacent together and coupled to the first leadframe. The two first pins are coupled to the source of the second power transistor. The two first pins are connected together through a conductive region for increasing capability of loading current. The plurality of first wires is coupled between the source of the second power transistor and the first pin to decrease the internal resistance of the second power transistor. The plurality of second wires is coupled between the first leadframe and the source of the first power transistor to decrease the internal resistance of the first power transistor.

    摘要翻译： 包装结构包括第一引线框架，第二引线框架，两个接地引脚，两个第一引脚，多个第一布线，多个第二布线和封装主体。 第二引线框架耦合到第一功率晶体管和第二功率晶体管的漏极。 两个接地引脚相邻在一起并耦合到第一引线框。 两个第一引脚耦合到第二功率晶体管的源极。 两个第一引脚通过导电区域连接在一起，以增加负载电流的能力。 多个第一布线耦合在第二功率晶体管的源极和第一引脚之间，以降低第二功率晶体管的内部电阻。 多个第二布线耦合在第一引线框架和第一功率晶体管的源极之间，以降低第一功率晶体管的内部电阻。