公开(公告)号：US20080120828A1

公开(公告)日：2008-05-29

申请号：US11564241

申请日：2006-11-28

申请人： Adam J. Whitworth ,  Wenjiang Zeng

发明人： Adam J. Whitworth ,  Wenjiang Zeng

IPC分类号： H01F7/06 ,  H05K3/20

CPC分类号： H01F17/0006 ,  H01F41/041 ,  H01L23/5227 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49128 ,  H01L2924/00

摘要： There is provided a method of making two electrically separated inductors using deposition and wet-etching techniques, which inductors are formed by interwinding one of the inductors within the other inductor on the same planar level. In still another aspect of the invention, there is provided a method of making various levels inductors, each level having at least two electrically separated inductors, using deposition and wet-etching techniques. The inductors on each planar level are formed by interwinding one of the inductors within the other inductor, and then stacking these in a preferred manner. In still another aspect, there is provided a manner of connecting together inductors formed according to the above methods in order to achieve various inductor configurations.

摘要翻译： 提供了一种使用沉积和湿蚀刻技术制造两个电分离的电感器的方法，该电感器通过在相同的平面电平上相互缠绕在另一个电感器内的一个电感器而形成。 在本发明的另一方面，提供了一种使用沉积和湿蚀刻技术制造各种电感电感器的方法，每个电平器具有至少两个电分离的电感器。 每个平面电平上的电感器通过相互缠绕另一个电感器内的一个电感器形成，然后以优选的方式堆叠这些电感器。 另一方面，提供了将根据上述方法形成的电感器连接在一起以实现各种电感器构造的方式。

公开(公告)号：US06556040B2

公开(公告)日：2003-04-29

申请号：US10210771

申请日：2002-07-31

申请人： Adam J. Whitworth

发明人： Adam J. Whitworth

IPC分类号： H03K1716

CPC分类号： H04L25/0298 ,  H04L25/0272

摘要： An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.

公开(公告)号：US08327523B2

公开(公告)日：2012-12-11

申请号：US11564241

申请日：2006-11-28

申请人： Adam J. Whitworth ,  Wenjiang Zeng

发明人： Adam J. Whitworth ,  Wenjiang Zeng

IPC分类号： H01F7/06

CPC分类号： H01F17/0006 ,  H01F41/041 ,  H01L23/5227 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49128 ,  H01L2924/00

摘要： There is provided a method of making two electrically separated inductors using deposition and wet-etching techniques, which inductors are formed by interwinding one of the inductors within the other inductor on the same planar level. In still another aspect of the invention, there is provided a method of making various levels inductors, each level having at least two electrically separated inductors, using deposition and wet-etching techniques. The inductors on each planar level are formed by interwinding one of the inductors within the other inductor, and then stacking these in a preferred manner. In still another aspect, there is provided a manner of connecting together inductors formed according to the above methods in order to achieve various inductor configurations.

摘要翻译： 提供了一种使用沉积和湿蚀刻技术制造两个电分离的电感器的方法，该电感器通过在相同的平面电平上相互缠绕在另一个电感器内的一个电感器而形成。 在本发明的另一方面，提供了一种使用沉积和湿蚀刻技术制造各种电感电感器的方法，每个电平器具有至少两个电分离的电感器。 每个平面电平上的电感器通过相互缠绕另一个电感器内的一个电感器形成，然后以优选的方式堆叠这些电感器。 另一方面，提供了将根据上述方法形成的电感器连接在一起以实现各种电感器构造的方式。

公开(公告)号：US06329837B1

公开(公告)日：2001-12-11

申请号：US09705595

申请日：2000-11-02

申请人： Adam J. Whitworth ,  Dominick Richiuso

发明人： Adam J. Whitworth ,  Dominick Richiuso

IPC分类号： H03K1716

CPC分类号： H04L25/0298 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/029

摘要： An active termination circuit for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage.

摘要翻译： 描述了用于在电子设备中的总线上夹紧信号的有源终端电路。 有源终端电路被配置为将总线上的信号钳位到第一参考电压电平和第二参考电压电平之一。 在一个实施例中，有源终端电路包括耦合到具有底部钳位晶体管控制节点的第一电位的底部钳位晶体管，被布置用于以大约第一参考电压钳位信号。 有源终端电路还包括耦合到具有顶部钳位晶体管控制节点的第二电位的顶部钳位晶体管，用于在大约第二参考电压下钳位信号。

公开(公告)号：US06323676B1

公开(公告)日：2001-11-27

申请号：US09706239

申请日：2000-11-02

申请人： Adam J. Whitworth ,  Dominick Richiuso

发明人： Adam J. Whitworth ,  Dominick Richiuso

IPC分类号： H03K1716

CPC分类号： H04L25/0298 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/029

摘要： An active termination circuit for protecting a node against an ESD voltage spike is described. The ESD protection circuit includes a bottom ESD protection transistor having a first node coupled to a first potential and a bottom ESD protection transistor intrinsic diode reverse biasedly coupling said node to a first reference voltage supply and a bottom threshold reference transistor coupled to the first reference voltage supply. The bottom threshold reference transistor provides a first bias voltage to the bottom ESD protection transistor gate that biases the bottom clamping transistor gate at about a first threshold voltage from the first reference voltage representing a threshold voltage of said bottom ESD protection transistor. The circuit also includes a top ESD protection transistor having a second node coupled to a second potential and a top ESD protection transistor intrinsic diode reverse biasedly coupling the node to a second reference voltage supply and a top threshold reference transistor coupled to the second reference voltage supply. The top threshold reference transistor provides a second bias voltage to the top ESD protection transistor gate that biases the top clamping transistor gate at about a second threshold voltage below the second reference voltage that represents a threshold voltage of said top ESD protection transistor.

摘要翻译： 描述了用于保护节点免受ESD电压尖峰的有源终端电路。 ESD保护电路包括底部ESD保护晶体管，其具有耦合到第一电位的第一节点和底部ESD保护晶体管本征二极管反向偏置地将所述节点耦合到第一参考电压源和耦合到第一参考电压的底部阈值参考晶体管 供应。 底部阈值参考晶体管向底部ESD保护晶体管栅极提供第一偏置电压，该第一偏置电压以大约第一阈值电压的方式将底部钳位晶体管栅极从表示所述底部ESD保护晶体管的阈值电压的第一参考电压偏置。 电路还包括顶部ESD保护晶体管，其具有耦合到第二电位的第二节点和顶部ESD保护晶体管本征二极管反向偏置地将节点耦合到第二参考电压源，以及耦合到第二参考电压源的顶部阈值参考晶体管 。 顶部阈值参考晶体管向顶部ESD保护晶体管栅极提供第二偏置电压，该栅极在高于表示所述顶部ESD保护晶体管的阈值电压的第二参考电压的约第二阈值电压处偏压顶部钳位晶体管栅极。

公开(公告)号：US20080258263A1

公开(公告)日：2008-10-23

申请号：US11738176

申请日：2007-04-20

申请人： Harry Yue Gee ,  Adam J. Whitworth ,  Umesh Sharma

发明人： Harry Yue Gee ,  Adam J. Whitworth ,  Umesh Sharma

IPC分类号： H01L29/866 ,  G05F1/00 ,  H01L21/20

CPC分类号： H01L29/866 ,  H01L27/0255 ,  H01L29/66106

摘要： A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability.

摘要翻译： 一种制造N + / P +齐纳二极管的方法，其中反向击穿以受控和均匀的方式发生，导致改进的操作速度和电流处理能力的增加。

公开(公告)号：US06326805B1

公开(公告)日：2001-12-04

申请号：US09705520

申请日：2000-11-02

申请人： Adam J. Whitworth ,  Dominick Richiuso

发明人： Adam J. Whitworth ,  Dominick Richiuso

IPC分类号： H03K1716

CPC分类号： H04L25/0298 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/029

摘要： An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage.

摘要翻译： 描述了用于钳位电子设备中的传输线上的信号的有源终端电路。 有源终端电路被配置为将传输线上的信号钳位到第一参考电压电平和第二参考电压电平之一。 在一个实施例中，有源终端电路包括耦合到具有底部钳位晶体管控制节点的第一电位的底部钳位晶体管，用于将信号约束在约第一参考电压处。 有源终端电路还包括耦合到具有顶部钳位晶体管控制节点的第二电位的顶部钳位晶体管，用于在大约第二参考电压下钳位信号。

公开(公告)号：US06326804B1

公开(公告)日：2001-12-04

申请号：US09705423

申请日：2000-11-02

申请人： Adam J. Whitworth ,  Dominick Richiuso

发明人： Adam J. Whitworth ,  Dominick Richiuso

IPC分类号： H03K1716

CPC分类号： H04L25/0298 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/029

摘要： An active termination circuit having localized potential supplies for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first localized potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second localized potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage. Any voltage excursions at the first localized potential does not affect the first localized reference voltage, and vice versa and any voltage excursions at the second localized potential does not affect the second localized reference voltage, and vice versa.

摘要翻译： 描述了具有用于钳位电子设备中的传输线上的信号的局部电位电源的有源终端电路。 有源终端电路被配置为将传输线上的信号钳位到第一参考电压电平和第二参考电压电平之一。 在一个实施例中，有源终端电路包括耦合到第一局部化电位的底部钳位晶体管，其具有底部钳位晶体管控制节点，用于以大约第一参考电压钳位信号。 有源终端电路还包括耦合到第二局部化电位的顶部钳位晶体管，其具有顶部钳位晶体管控制节点，该顶部钳位晶体管控制节点用于以大约第二参考电压钳位信号 在第一局部电位处的任何电压偏移不影响第一局部参考电压，反之亦然，并且在第二局部电位处的任何电压偏移不影响第二局部参考电压，反之亦然。

公开(公告)号：US06323675B1

公开(公告)日：2001-11-27

申请号：US09705425

申请日：2000-11-02

申请人： Adam J. Whitworth ,  Dominick Richiuso

发明人： Adam J. Whitworth ,  Dominick Richiuso

IPC分类号： H03K19003

CPC分类号： H04L25/0298 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/029

摘要： An active termination circuit for clamping a signal on a transmission line in an electronic device in a tri-state mode is described. The active circuit includes a tri-state output buffer and a bottom clamping transistor coupled to GND and the tri-state output buffer having a bottom clamping transistor control node arranged for clamping the signal at about GND. A bottom threshold reference transistor coupled to a first reference voltage supply configured to supply a first reference voltage. The bottom threshold reference transistor provides a first bias voltage to the bottom clamping transistor control node that biases the bottom clamping transistor control node at about a first threshold voltage above GND where the first threshold voltage represents a threshold voltage of the bottom clamping transistor. A top clamping transistor coupled to VDD and the tri-state output buffer having a top clamping transistor control node arranged for clamping said signal at about VDD and a top threshold reference transistor coupled to a second reference voltage supply configured to supply a second reference voltage. The top threshold reference transistor provides a second bias voltage to the top clamping transistor control node that biases the top clamping transistor control node at about a second threshold voltage from VDD where the second threshold voltage represents a top clamping transistor threshold voltage.

摘要翻译： 描述了用于以三态模式在电子设备中的传输线上夹紧信号的有源终端电路。 有源电路包括耦合到GND的三态输出缓冲器和底部钳位晶体管，并且三态输出缓冲器具有用于将信号钳位在大约GND处的底部钳位晶体管控制节点。 耦合到被配置为提供第一参考电压的第一参考电压源的底部阈值参考晶体管。 底部阈值参考晶体管向底部钳位晶体管控制节点提供第一偏置电压，其将底部钳位晶体管控制节点偏置在高于GND的第一阈值电压处，其中第一阈值电压表示底部钳位晶体管的阈值电压。 耦合到VDD的顶部钳位晶体管和具有顶部钳位晶体管控制节点的三态输出缓冲器，所述顶部钳位晶体管控制节点布置成用于将所述信号钳位在大约VDD处;以及顶部阈值参考晶体管，耦合到被配置为提供第二参考电压的第二参考电压源 顶部阈值参考晶体管向顶部钳位晶体管控制节点提供第二偏置电压，该偏置电压从VDD的大约第二阈值电压偏置顶部钳位晶体管控制节点，其中第二阈值电压表示顶部钳位晶体管阈值电压。

公开(公告)号：US07321241B1

公开(公告)日：2008-01-22

申请号：US11424535

申请日：2006-06-15

申请人： Chadwick N. Marak ,  Jeffrey C. Dunnihoo ,  Adam J. Whitworth

发明人： Chadwick N. Marak ,  Jeffrey C. Dunnihoo ,  Adam J. Whitworth

IPC分类号： H03K19/0175

CPC分类号： H03K19/0005

摘要： The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.

摘要翻译： 本发明涉及在至少一个方向上具有压摆率控制的双向缓冲器。 本发明还涉及一种在至少一个方向上以压摆率控制双向传输信号的方法。