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1.发明申请公开(公告)号：US20060067369A1
公开(公告)日：2006-03-30
申请号：US10957527
申请日：2004-09-30
CPC分类号： H04J3/0605 , H04J3/0614
摘要： A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats perform a search for a differential frame alignment sequence (FAS) to frame-align the received digital stream and determine the polarity of the stream. Embodiments of the invention are compatible with Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats.
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公开(公告)号：US09100506B2
公开(公告)日：2015-08-04
申请号：US13319248
申请日：2010-06-10
CPC分类号： H04M11/062 , H04B3/32 , H04L25/03343 , H04L2025/03426
摘要： In one embodiment, the line termination card includes a data output terminal configured to output a data sequence. The card further includes a vectoring entity configured to parse and encode the data sequence into frequency samples according to a carrier loading parameter, configured to scale the frequency samples into scaled frequency samples according to a carrier scaling parameter, and, configured to process the scaled frequency samples for crosstalk compensation. A controller is configured to adjust the carrier loading parameter and the carrier scaling parameter, and a forwarder is coupled to the data output terminal and to the controller. The forwarder is configured to forward the data sequence, the carrier loading parameter and the carrier scaling parameter towards a further line termination card.
摘要翻译： 在一个实施例中，线路终端卡包括被配置为输出数据序列的数据输出端子。 卡还包括向量实体，其被配置为根据载波负载参数将数据序列解析和编码为频率样本，其被配置为根据载波缩放参数将频率样本缩放为缩放的频率样本，并且被配置为处理缩放频率 采样串扰补偿。 控制器被配置为调整载波负载参数和载波缩放参数，并且转发器耦合到数据输出端子和控制器。 转发器被配置为向另一个线路终端卡转发数据序列，载波加载参数和载波缩放参数。
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公开(公告)号：US20120057693A1
公开(公告)日：2012-03-08
申请号：US13319248
申请日：2010-06-10
CPC分类号： H04M11/062 , H04B3/32 , H04L25/03343 , H04L2025/03426
摘要： In one embodiment, the line termination card includes a data output terminal configured to output a data sequence. The card further includes a vectoring entity configured to parse and encode the data sequence into frequency samples according to a carrier loading parameter, configured to scale the frequency samples into scaled frequency samples according to a carrier scaling parameter, and, configured to process the scaled frequency samples for crosstalk compensation. A controller is configured to adjust the carrier loading parameter and the carrier scaling parameter, and a forwarder is coupled to the data output terminal and to the controller. The forwarder is configured to forward the data sequence, the carrier loading parameter and the carrier scaling parameter towards a further line termination card.
摘要翻译： 在一个实施例中，线路终端卡包括被配置为输出数据序列的数据输出端子。 卡还包括向量实体，其被配置为根据载波负载参数将数据序列解析和编码为频率样本，其被配置为根据载波缩放参数将频率样本缩放为缩放的频率样本，并且被配置为处理缩放频率 采样串扰补偿。 控制器被配置为调整载波负载参数和载波缩放参数，并且转发器耦合到数据输出端子和控制器。 转发器被配置为向另一个线路终端卡转发数据序列，载波加载参数和载波缩放参数。
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公开(公告)号：US20050262402A1
公开(公告)日：2005-11-24
申请号：US10848496
申请日：2004-05-18
申请人： Raul Ballester , Adriaan De Lind Van Wijngaarden , Ralf Dohmen , Bernd Dotterweich , Swen Wunderlich
发明人： Raul Ballester , Adriaan De Lind Van Wijngaarden , Ralf Dohmen , Bernd Dotterweich , Swen Wunderlich
IPC分类号： G06F11/00
CPC分类号： H04L1/241
摘要： Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.
摘要翻译： 通过将从一组基本上不相关的位错误发生器输出的G位的第一错误模式随机分配到N位的第二错误模式中，产生用于高速数据系统的位错误模式，其中G和N是整数，G是 小于或等于N.在一个实施例中，G位错误发生器产生每位周期的G位错误模式。 每个位错误发生器以规定的位错误率运行。 分配元素随机重新排列在N位分组内的单个位周期期间产生的G位的顺序和位置。 N位组对应于可以组合错误位的N个连续的数据位。 每个位错误发生器可以由线性反馈移位寄存器或其等效物来实现。 每个线性反馈移位寄存器可以使用不同的原始多项式和不同的长度。 此外，利用来自少于所有移位寄存器级的输出来产生每个错误位。
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