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    Noisy channel emulator for high speed data
    2.
    发明申请
    Noisy channel emulator for high speed data 有权
    噪声通道模拟器用于高速数据

    公开(公告)号：US20050262402A1

    公开(公告)日：2005-11-24

    申请号：US10848496

    申请日：2004-05-18

    申请人： Raul Ballester ,  Adriaan De Lind Van Wijngaarden ,  Ralf Dohmen ,  Bernd Dotterweich ,  Swen Wunderlich

    发明人： Raul Ballester ,  Adriaan De Lind Van Wijngaarden ,  Ralf Dohmen ,  Bernd Dotterweich ,  Swen Wunderlich

    IPC分类号： G06F11/00

    CPC分类号： H04L1/241

    摘要： Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.

    摘要翻译： 通过将从一组基本上不相关的位错误发生器输出的G位的第一错误模式随机分配到N位的第二错误模式中，产生用于高速数据系统的位错误模式，其中G和N是整数，G是 小于或等于N.在一个实施例中，G位错误发生器产生每位周期的G位错误模式。 每个位错误发生器以规定的位错误率运行。 分配元素随机重新排列在N位分组内的单个位周期期间产生的G位的顺序和位置。 N位组对应于可以组合错误位的N个连续的数据位。 每个位错误发生器可以由线性反馈移位寄存器或其等效物来实现。 每个线性反馈移位寄存器可以使用不同的原始多项式和不同的长度。 此外，利用来自少于所有移位寄存器级的输出来产生每个错误位。

    Noisy channel emulator for high speed data
    3.
    发明授权
    Noisy channel emulator for high speed data 有权
    噪声通道模拟器用于高速数据

    公开(公告)号：US07426666B2

    公开(公告)日：2008-09-16

    申请号：US10848496

    申请日：2004-05-18

    申请人： Raul Benet Ballester ,  Adriaan J. De Lind Van Wijngaarden ,  Ralf Dohmen ,  Bernd Dotterweich ,  Swen Wunderlich

    发明人： Raul Benet Ballester ,  Adriaan J. De Lind Van Wijngaarden ,  Ralf Dohmen ,  Bernd Dotterweich ,  Swen Wunderlich

    IPC分类号： G01R31/28

    CPC分类号： H04L1/241

    摘要： Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.

    摘要翻译： 通过将从一组基本上不相关的位错误发生器输出的G位的第一错误模式随机分配到N位的第二错误模式中，产生用于高速数据系统的位错误模式，其中G和N是整数，G是 小于或等于N.在一个实施例中，G位错误发生器产生每位周期的G位错误模式。 每个位错误发生器以规定的位错误率运行。 分配元素随机重新排列在N位分组内的单个位周期期间产生的G位的顺序和位置。 N位组对应于可以组合错误位的N个连续的数据位。 每个位错误发生器可以由线性反馈移位寄存器或其等效物来实现。 每个线性反馈移位寄存器可以使用不同的原始多项式和不同的长度。 此外，利用来自少于所有移位寄存器级的输出来产生每个错误位。

    Forward error correction for high speed optical transmission systems
    8.
    发明授权
    Forward error correction for high speed optical transmission systems 有权
    高速光传输系统的前向纠错

    公开(公告)号：US06683855B1

    公开(公告)日：2004-01-27

    申请号：US09143781

    申请日：1998-08-31

    申请人： Mark Aldo Bordogna ,  Ralf Dohmen ,  Wolfram Sturm

    发明人： Mark Aldo Bordogna ,  Ralf Dohmen ,  Wolfram Sturm

    IPC分类号： H04J116

    CPC分类号： H04L1/0057 ,  H04J3/14 ,  H04J3/1611 ,  H04J2203/0089 ,  H04L1/0043 ,  H04L1/0083

    摘要： Memory requirements and processing delays associated with the application of forward error correction in high speed optical transmissions are substantially reduced by mapping a forward error correction code on a row-by-row basis into unused overhead bytes in a high bit rate signal frame. By applying the forward error correction code to an entire row of the signal frame on a row by row basis, approximately one row needs to be stored at a time thereby reducing the total memory requirements for forward error correction processing. Using SONET as an exemplary application, approximately {fraction (1/9)}th of the entire SONET frame (e.g., one of nine rows) needs to be buffered for forward error correction processing. In an illustrative embodiment, four forward error correction (FEC) blocks are provided for each row for a total of 36 FEC blocks for a frame. Each FEC block comprises four bytes of correction bits for a total of 32 correction bits. These 32 correction bits are mapped to unused overhead and are used for correcting errors in one block of one row of a signal frame, wherein one block covers ¼th of the row. Other unused overhead bytes in the row can be used to carry error detection codes for detecting multiple errors in a row to determine when forward error correction should be disabled. For example, if a single bit error correcting code is employed, then error correction can be disabled to avoid false corrections if more than one error is detected.

    摘要翻译： 通过将高速率光传输中的前向纠错码逐行地映射到高比特率信号帧中的未使用的开销字节，大大减少了与高速光传输中的前向纠错应用相关联的存储器要求和处理延迟。 通过逐行地将前向纠错码应用于信号帧的整个行，需要一次存储大约一行，从而减少前向纠错处理的总存储器要求。 使用SONET作为示例性应用，大约{部分（整个SONET帧的1/9（例如，九行中的一个）需要被缓冲用于前向纠错处理）在说明性实施例中，四个前向纠错（FEC）块 为每帧提供总共36个FEC块，每个FEC块包含四个字节的校正位，总共32个校正位，这32个校正位映射到未使用的开销，用于校正一个错误 一行信号帧的块，其中一个块覆盖该行的第十四行，该行中的其他未使用的开销字节可用于携带用于检测一行中的多个错误的错误检测码，以确定何时应禁用前向纠错。 例如，如果采用单个位错误校正码，则如果检测到多于一个错误，则可以禁用错误校正以避免错误校正。

    High speed syndrome-based FEC encoder and system using same
    9.
    发明申请
    High speed syndrome-based FEC encoder and system using same 有权
    基于高速综合征的FEC编码器和系统使用相同

    公开(公告)号：US20050210353A1

    公开(公告)日：2005-09-22

    申请号：US11129193

    申请日：2005-05-13

    申请人： Ralf Dohmen ,  Timo Schuering ,  Leilei Song ,  Meng-Lin Yu

    发明人： Ralf Dohmen ,  Timo Schuering ,  Leilei Song ,  Meng-Lin Yu

    IPC分类号： H03M13/15 ,  H04L1/00 ,  G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00

    CPC分类号： H03M13/1595 ,  H03M13/1515 ,  H03M13/1535 ,  H03M13/158

    摘要： A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

    摘要翻译： 公开了一种解码器，编码器和对应系统，用于提供基于错误校正码的纠错码的快速前向纠错（FEC）解码和编码。 三并行处理由系统的元件执行。 更具体地，在说明性实施例中，解码器执行三并行校正子生成和错误确定和计算，并且编码器执行三并行编码。 低功耗和复杂度技术用于节省成本和功耗，同时提供相对高速的编码和解码。

    High Speed Syndrome-Based FEC Encoder and System Using Same
    10.
    发明申请
    High Speed Syndrome-Based FEC Encoder and System Using Same 有权
    基于高速综合征的FEC编码器和使用相同的系统

    公开(公告)号：US20090150754A1

    公开(公告)日：2009-06-11

    申请号：US12370739

    申请日：2009-02-13

    申请人： Ralf Dohmen ,  Timo Frithjof Schuering ,  Leilei Song ,  Meng-Lin Mark Yu

    发明人： Ralf Dohmen ,  Timo Frithjof Schuering ,  Leilei Song ,  Meng-Lin Mark Yu

    IPC分类号： H03M13/07 ,  G06F11/10

    CPC分类号： H03M13/1595 ,  H03M13/1515 ,  H03M13/1535 ,  H03M13/158

    摘要： A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

    摘要翻译： 公开了一种解码器，编码器和对应系统，用于提供基于错误校正码的纠错码的快速前向纠错（FEC）解码和编码。 三并行处理由系统的元件执行。 更具体地，在说明性实施例中，解码器执行三并行校正子生成和错误确定和计算，并且编码器执行三并行编码。 低功耗和复杂度技术用于节省成本和功耗，同时提供相对高速的编码和解码。