公开(公告)号：US20090321848A1

公开(公告)日：2009-12-31

申请号：US12556003

申请日：2009-09-09

申请人： Kazuhito Ichinose ,  Akie Yutani

发明人： Kazuhito Ichinose ,  Akie Yutani

IPC分类号： H01L23/48 ,  H01L29/78

CPC分类号： H01L21/823443 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.

摘要翻译： 根据本发明的制造半导体器件的方法包括以下步骤：将第一导电类型的第一杂质引入半导体衬底1的主表面以形成第一杂质区，引入第二导电类型的第二杂质形成 第二杂质区，在所述第一杂质区上形成第一硅化镍膜，在所述第二杂质区上形成第二硅化镍膜，通过使用混合气体除去形成在所述第一和第二硅化镍膜上的氧化膜， NH 3气体和含有氢元素的气体混合，在第一硅化镍膜上形成第一导电膜，在第二硅化镍膜上形成第二导电膜，除去氧化物膜。

公开(公告)号：US20060113676A1

公开(公告)日：2006-06-01

申请号：US11269799

申请日：2005-11-09

申请人： Kazuhito Ichinose ,  Akie Yutani

发明人： Kazuhito Ichinose ,  Akie Yutani

IPC分类号： H01L23/48

CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A barrier metal layer having a two-layer structure of a titanium film and a titanium nitride film is formed on the inner surface of a through hole. The titanium film and the titanium nitride film are formed on a main surface of an interlayer insulating film as well. In forming the barrier metal layer, a deposition device is used that is capable of high-directivity sputtering using a titanium target, and includes a substrate bias system biasing a semiconductor substrate to a high frequency voltage to attract sputter particles from the titanium target to the semiconductor substrate. This allows the titanium nitride film to be formed as an amorphous metal film.

摘要翻译： 在通孔的内表面上形成具有钛膜和氮化钛膜的两层结构的阻挡金属层。 钛膜和氮化钛膜也形成在层间绝缘膜的主表面上。 在形成阻挡金属层时，使用能够使用钛靶进行高指向性溅射的沉积装置，并且包括将半导体衬底偏压到高频电压的衬底偏置系统，以将溅射颗粒从钛靶吸引到 半导体衬底。 这样可以使氮化钛膜形成为非晶金属膜。

公开(公告)号：US20070161218A1

公开(公告)日：2007-07-12

申请号：US11619790

申请日：2007-01-04

申请人： Kazuhito Ichinose ,  Akie Yutani

发明人： Kazuhito Ichinose ,  Akie Yutani

IPC分类号： H01L21/265

CPC分类号： H01L21/823443 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.

摘要翻译： 根据本发明的制造半导体器件的方法包括以下步骤：将第一导电类型的第一杂质引入半导体衬底1的主表面以形成第一杂质区，引入第二导电类型的第二杂质形成 第二杂质区，在所述第一杂质区上形成第一硅化镍膜，在所述第二杂质区上形成第二硅化镍膜，通过使用混合气体除去形成在所述第一和第二硅化镍膜上的氧化膜， NH 3气体和含有氢元素的气体混合，并在第一硅化镍膜上形成第一导电膜，并在第二硅化镍膜上形成第二导电膜，氧化膜 删除。

公开(公告)号：US06686621B2

公开(公告)日：2004-02-03

申请号：US10196951

申请日：2002-07-18

申请人： Akie Yutani

发明人： Akie Yutani

IPC分类号： H01L2978

CPC分类号： H01L28/91 ,  H01L27/10855

摘要： A semiconductor device which includes a capacitor wherein the capacitance of the capacitor can be prevented from being lowered even in the case that the capacitor is miniaturized. A core insulating film having the core of the capacitor formed above a semiconductor substrate, a capacitor lower electrode formed so as to cover side surfaces of this core insulating film, a capacitor dielectric film formed so as to cover the surface of this capacitor lower electrode and the upper surface of the core insulating film and a capacitor upper electrode formed so as to cover the surface of this core insulating film are provided so that the bottom surface of the core insulating film is positioned lower than the bottom surface of the capacitor lower electrode.

摘要翻译： 包括电容器的半导体器件，其中即使在电容器小型化的情况下，也可以防止电容器的电容降低。 在半导体衬底上形成具有电容器芯的芯绝缘膜，形成为覆盖该芯绝缘膜的侧表面的电容器下电极，形成为覆盖该电容器下电极的表面的电容器电介质膜，以及 设置芯绝缘膜的上表面和形成为覆盖该芯绝缘膜的表面的电容器上电极，使得芯绝缘膜的底面位于比电容器下电极的底面低的位置。

公开(公告)号：US06344400B1

公开(公告)日：2002-02-05

申请号：US09539885

申请日：2000-03-31

申请人： Akie Yutani

发明人： Akie Yutani

IPC分类号： H01L2120

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L28/55

摘要： Referring to a capacitor having a capacitor dielectric film made of a high dielectric film, it is possible to obtain a method of manufacturing a semiconductor device capable of forming a fine storage node made of a noble metal. A polysilicon film is formed over a whole face of an interlayer insulating film (9), and is then subjected to anisotropic dry etching by using, as a mask, a resist having a predetermined opening pattern. Consequently, a polysilicon film (22a) is formed in contact with a plug layer (11). Next, a noble metal element is substituted for a silicon element contained in the polysilicon film (22a). Thus, it is possible to form a storage node (22) which has at least a surface made of the noble metal element and has the same three-dimensional configuration as the polysilicon film (22a) obtained before the substitution.

摘要翻译： 参考具有由高电介质膜制成的电容器电介质膜的电容器，可以获得能够形成由贵金属制成的精细储存节点的半导体器件的方法。 在层间绝缘膜（9）的整个表面上形成多晶硅膜，然后通过使用具有预定开口图案的抗蚀剂作为掩模，进行各向异性干蚀刻。 因此，形成与插塞层（11）接触的多晶硅膜（22a）。 接着，将贵金属元素代替包含在多晶硅膜（22a）中的硅元素。 因此，可以形成至少具有由贵金属元件制成的表面并且具有与替代之前获得的多晶硅膜（22a）相同的三维构造的存储节点（22）。

公开(公告)号：US08728853B2

公开(公告)日：2014-05-20

申请号：US13265513

申请日：2009-04-24

申请人： Akie Yutani ,  Yasutaka Nishioka

发明人： Akie Yutani ,  Yasutaka Nishioka

IPC分类号： H01L21/00

CPC分类号： H01L27/14685 ,  H01L27/14603 ,  H01L27/14605 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14689

摘要： By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.

摘要翻译： 通过选择性地各向异性地蚀刻形成为覆盖多个光电二极管的堆叠膜和MOS晶体管的栅极电极层，堆叠膜保留在多个光电二极管中的每一个上，以形成较低的抗反射涂层，并且堆叠膜保留在 栅电极层形成侧壁。 使用栅极电极层和侧壁作为掩模，引入杂质以形成MOS晶体管的源极/漏极区域。 在引入杂质之后，至少在较低的抗反射涂层上形成上部抗反射涂层。 蚀刻上部抗反射涂层和下部抗反射涂层中的至少一个，使得两个相应光电二极管上的抗反射涂层的厚度彼此不同。

公开(公告)号：US08058166B2

公开(公告)日：2011-11-15

申请号：US12903465

申请日：2010-10-13

申请人： Kazuhito Ichinose ,  Akie Yutani

发明人： Kazuhito Ichinose ,  Akie Yutani

IPC分类号： H01L21/4763

CPC分类号： H01L21/823443 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.

摘要翻译： 根据本发明的制造半导体器件的方法包括以下步骤：将第一导电类型的第一杂质引入半导体衬底1的主表面以形成第一杂质区，引入第二导电类型的第二杂质形成 第二杂质区，在所述第一杂质区上形成第一硅化镍膜，在所述第二杂质区上形成第二硅化镍膜，通过使用混合气体除去形成在所述第一和第二硅化镍膜上的氧化膜， NH 3气体和含有氢元素的气体混合，在第一硅化镍膜上形成第一导电膜，在第二硅化镍膜上形成第二导电膜，除去氧化物膜。

公开(公告)号：US20070173050A1

公开(公告)日：2007-07-26

申请号：US11655162

申请日：2007-01-19

申请人： Kazuhito Ichinose ,  Akie Yutani

发明人： Kazuhito Ichinose ,  Akie Yutani

IPC分类号： H01L21/44

CPC分类号： H01L21/76895 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76897

摘要： A barrier metal film such as a TiN film is formed in a contact hole or a via hole. Then, a W nucleation film is formed on the barrier metal film by CVD that reduces WF6 gas with B2H6 gas. Subsequently, a W plug is formed as a contact plug or a via plug on the W nucleation film by CVD.

摘要翻译： 在接触孔或通孔中形成诸如TiN膜的阻挡金属膜。 然后，通过用B 2 H 6气体减少WF 6气体的CVD在阻挡金属膜上形成W成核膜。 随后，通过CVD在W成核膜上形成W插塞作为接触塞或通孔塞。

公开(公告)号：US06746876B2

公开(公告)日：2004-06-08

申请号：US10310765

申请日：2002-12-06

申请人： Hiromi Itoh ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara ,  Akie Yutani ,  Tomonori Okudaira

发明人： Hiromi Itoh ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara ,  Akie Yutani ,  Tomonori Okudaira

IPC分类号： H01L218242

CPC分类号： H01L28/55 ,  H01L28/91

摘要： A method for manufacturing a capacitor is provided which can form a lower electrode having a high aspect ratio without suffering deterioration of the capacitor electric characteristics even when a platinum-group metal is adopted as the material of the lower electrode and a metal oxide having a high dielectric constant is adopted as the material of the dielectric film. Holes (8) that reach contact plugs (2) are formed in an insulating film (7). Then a dielectric film (9) is formed on the surfaces of the holes (8). Next the dielectric film (9) on the bottoms of the holes (8) are etched away to form holes (18) reaching the contact plugs (2). Lower electrodes (11) are then formed to fill the holes (8) and (18).

摘要翻译： 提供了一种用于制造电容器的方法，即使当采用铂族金属作为下电极的材料时，也可形成具有高纵横比的下电极，而不会降低电容器的电特性，并且具有高的金属氧化物 采用介电常数作为电介质膜的材料。 到达接触塞（2）的孔（8）形成在绝缘膜（7）中。 然后在孔（8）的表面上形成介电膜（9）。 接下来，蚀刻掉孔（8）的底部上的电介质膜（9），以形成到达接触塞（2）的孔（18）。 然后形成下电极（11）以填充孔（8）和（18）。

公开(公告)号：US06437968B1

公开(公告)日：2002-08-20

申请号：US09476781

申请日：1999-12-30

申请人： Akie Yutani

发明人： Akie Yutani

IPC分类号： H01G4228

CPC分类号： H01L28/75 ,  H01L28/55

摘要： An oxide dielectric film (7) is formed of barium strontium titanate to have a thickness of 300 to 600 Å, and a first platinum layer (81) is deposited thereon by, e.g., sputtering at a temperature not higher than 250° C. to have a thickness of 250 to 500 Å. Further, a second platinum layer (82) is deposited on the first platinum layer (81) by, e.g., sputtering at a temperature of 250 to 500° C. to have a thickness of 250 to 500 Å. Since the first platinum layer (81) has less grain boundary and is hard to connect to that of the second platinum layer (82), with less grain boundary diffusion caused, even if a hydrogen sintering of an aluminum interconnection layer (11) is performed, reduction species are unlikely to reach the oxide dielectric film (7) through the grain boundary. That suppresses deterioration of the oxide dielectric film (7) to avoid an increase of leak current therein. Moreover, since the surface area of the second platinum layer (82) increases, the adherence between the second platinum layer (82) and an interlayer insulating film (10) provided thereon is improved.

摘要翻译： 氧化物电介质膜（7）由钛酸钡锶形成，厚度为300〜600，第一铂层（81）通过例如在不高于250℃的温度下溅射淀积到第一铂层 具有250至500埃的厚度。 此外，通过例如在250-500℃的温度下溅射，在第一铂层（81）上沉积第二铂层（82）以具有250〜500的厚度。 由于第一铂层（81）具有较少的晶界并难以与第二铂层（82）连接，所以即使进行了铝互连层（11）的氢烧结，也产生较少的晶界扩散 ，还原物质不可能通过晶界到达氧化物介电膜（7）。 抑制氧化物绝缘膜（7）的劣化，以防止其中的漏电流增加。 此外，由于第二铂层（82）的表面积增加，所以第二铂层（82）与设置在其上的层间绝缘膜（10）之间的粘附性提高。