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    Binary data transmission on a single information channel
    1.
    发明授权
    Binary data transmission on a single information channel 失效
    单个信息通道上的二进制数据传输

    公开(公告)号：US07206362B2

    公开(公告)日：2007-04-17

    申请号：US09779038

    申请日：2001-02-08

    申请人： Alan Gene Gara

    发明人： Alan Gene Gara

    IPC分类号： H03D1/00 ,  H04L27/06

    CPC分类号： H04L25/4904 ,  H04L25/4923

    摘要： In the invention, it becomes possible to extract all clock information data processing data by simultaneously comparing first, second and third voltage levels to each data bit in clocked time increments wherein the magnitude of the increments is such that each binary data bit is in two of the three voltage levels and all data bits change each clock cycle, so that reconstructed signals of the binary information only may then be assembled based on a signal amplitude that is greater than a low threshold value that is less than the transition between the first and the second of the voltage levels and is less than a high threshold that is greater than the transition between the second and the third voltage levels. The reconstructed data signals are further shaped to be precise in timing, free of skewing and within the system clock.

    摘要翻译： 在本发明中，通过将时钟时间增量中的每个数据位同时比较第一，第二和第三电压电平，可以提取所有时钟信息数据处理数据，其中增量的大小使得每个二进制数据位为 三个电压电平和所有数据位改变每个时钟周期，从而可以基于大于低阈值的信号幅度来组装二进制信息的重建信号，该低阈值小于第一和第 并且小于高于第二和第三电压电平之间的转变的高阈值。 重建的数据信号进一步成形为在时序上精确，没有偏斜并且在系统时钟内。

    AC drive cross point adjust method and apparatus
    2.
    发明授权
    AC drive cross point adjust method and apparatus 失效
    交流变频器交叉点调整方法及装置

    公开(公告)号：US06518794B2

    公开(公告)日：2003-02-11

    申请号：US09818796

    申请日：2001-03-27

    申请人： Paul William Coteus ,  Alan Gene Gara

    发明人： Paul William Coteus ,  Alan Gene Gara

    IPC分类号： H03K1900

    CPC分类号： H03K19/00384 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C2207/2254 ,  H03K19/00323

    摘要： The invention teaches a technique for A C equilibration of the signaling levels and time of 1—>h and h—>1 transitions of CMOS drivers as received at CMOS receivers, so as to improve the rate at which data can be communicated between two CMOS devices. It permits minimization of a switching delay in Double Data Rate Dram memories.

    摘要翻译： 本发明教导了一种用于在CMOS接收器处接收的CMOS驱动器的信号电平和信号电平和时间的平衡技术，以便提高在两个CMOS器件之间传送数据的速率 它允许最小化双数据速率Dram存储器中的切换延迟。