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26 条记录 (耗时 0.037 秒)

    Sinusoidal clock signal distribution using resonant transmission lines
    3.
    发明授权
    Sinusoidal clock signal distribution using resonant transmission lines 失效
    使用谐振传输线的正弦时钟信号分配

    公开(公告)号：US6098176A

    公开(公告)日：2000-08-01

    申请号：US16788

    申请日：1998-01-30

    申请人： Paul William Coteus ,  Daniel Mark Dreps ,  Frank Ferraiolo ,  Gerard Vincent Kopcsay ,  Todd Edward Takken

    发明人： Paul William Coteus ,  Daniel Mark Dreps ,  Frank Ferraiolo ,  Gerard Vincent Kopcsay ,  Todd Edward Takken

    IPC分类号： G06F1/10 ,  G06F1/12

    CPC分类号： G06F1/10

    摘要： A clock signal distribution system is disclosed for providing synchronous clock signals to a plurality of electronic circuit devices. The system includes a clock signal generator means for providing a single frequency sinusoidal clock signal output and a plurality of electronic circuit devices. A clock signal distribution network including interconnected resonant segments of a transmission line 13 connected to the clock signal of the clock signal generator and to the plurality of electronic circuit devices for providing separate synchronous, phase aligned clock signals to the electronic circuit devices. The transmission line segments have lengths matched to the clock signal frequency wavelengths to eliminate clock signal distribution problems such as skew, jitter and pulse distortions.

    摘要翻译： 公开了一种用于向多个电子电路装置提供同步时钟信号的时钟信号分配系统。 该系统包括用于提供单频正弦时钟信号输出的时钟信号发生器装置和多个电子电路装置。 时钟信号分配网络，包括连接到时钟信号发生器的时钟信号的传输线路13的互连谐振段，以及多个电子电路装置，用于向电子电路装置提供单独的同步相位对准的时钟信号。 传输线段具有与时钟信号频率波长匹配的长度，以消除诸如偏斜，抖动和脉冲失真的时钟信号分配问题。

    Variable voltage CMOS off-chip driver and receiver circuits
    4.
    发明授权
    Variable voltage CMOS off-chip driver and receiver circuits 失效
    可变电压CMOS片外驱动和接收电路

    公开(公告)号：US08604828B1

    公开(公告)日：2013-12-10

    申请号：US08657849

    申请日：1996-05-31

    申请人： Harry Randall Bickford ,  Paul William Coteus ,  Robert Heath Dennard ,  Daniel Mark Dreps ,  Gerard Vincent Kopcsay

    发明人： Harry Randall Bickford ,  Paul William Coteus ,  Robert Heath Dennard ,  Daniel Mark Dreps ,  Gerard Vincent Kopcsay

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/0005 ,  H03K19/018521 ,  H03K19/018585

    摘要： A structure is described having a plurality of electronic devices with the same or different internal CMOS voltages; an interconnection between two or more of the electronic devices; driver and receiver circuits which provide selectable input/output voltage levels for interfacing with several generations of CMOS technology, thus allowing chips fabricated in such technologies to communicate using a signal voltage range most suitable for each chip; Circuitry for selecting or adjusting the type of receiver circuit used, thus allowing either the use of a differential comparator circuit with an externally supplied reference voltage, or alternatively, the use of an inverter style receiver with an adjustable threshold, the selection being accomplished by setting the external reference to a predetermined voltage; Circuitry for selecting or adjusting the switching threshold of the inverter receiver circuit, which enables the threshold to be set appropriately for a given input signal voltage range.

    摘要翻译： 描述了具有多个具有相同或不同的内部CMOS电压的电子器件的结构; 两个或多个电子设备之间的互连; 驱动器和接收器电路，其提供用于与几代CMOS技术接口的可选输入/输出电压电平，从而允许以这种技术制造的芯片使用最适合于每个芯片的信号电压范围进行通信; 用于选择或调整所使用的接收器电路的类型的电路，从而允许使用具有外部提供的参考电压的差分比较器电路，或者使用具有可调阈值的逆变器式接收器，该选择通过设置 外部参考预定电压; 用于选择或调整逆变器接收器电路的开关阈值的电路，其使得能够针对给定输入信号电压范围适当地设定阈值。

    AC drive cross point adjust method and apparatus
    6.
    发明授权
    AC drive cross point adjust method and apparatus 失效
    交流变频器交叉点调整方法及装置

    公开(公告)号：US06518794B2

    公开(公告)日：2003-02-11

    申请号：US09818796

    申请日：2001-03-27

    申请人： Paul William Coteus ,  Alan Gene Gara

    发明人： Paul William Coteus ,  Alan Gene Gara

    IPC分类号： H03K1900

    CPC分类号： H03K19/00384 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C2207/2254 ,  H03K19/00323

    摘要： The invention teaches a technique for A C equilibration of the signaling levels and time of 1—>h and h—>1 transitions of CMOS drivers as received at CMOS receivers, so as to improve the rate at which data can be communicated between two CMOS devices. It permits minimization of a switching delay in Double Data Rate Dram memories.

    摘要翻译： 本发明教导了一种用于在CMOS接收器处接收的CMOS驱动器的信号电平和信号电平和时间的平衡技术，以便提高在两个CMOS器件之间传送数据的速率 它允许最小化双数据速率Dram存储器中的切换延迟。

    Smart memory interface
    7.
    发明授权
    Smart memory interface 失效
    智能内存界面

    公开(公告)号：US06292903B1

    公开(公告)日：2001-09-18

    申请号：US09106639

    申请日：1998-06-29

    申请人： Paul William Coteus ,  Daniel Mark Dreps ,  Frank Ferraiolo

    发明人： Paul William Coteus ,  Daniel Mark Dreps ,  Frank Ferraiolo

    IPC分类号： G06F104

    CPC分类号： G06F13/1689

    摘要： A method and apparatus are disclosed for initiating a start-up operation of a system (1′) having a master device (1) and a slave device (14a-14n). The method comprises steps of: A) exercising the slave device (14a-14n) using the master device (1) to determine a temporal range within which temporal relationships of electrical signals need to be set in order to operate the system (1′) without error; B) setting the temporal relationships of the electrical signals so as to be within the determined temporal range; and C) storing a record of the determined temporal range, for subsequent use in operating the system (1′). In one embodiment of the invention, the system (1′) includes a memory control system of a computer system (1″), and the slave device (14a-14n) includes memory devices of the computer system (1″). The method of the invention substantially compensates for any differences in times of arrival for data being transferred from the master device (1) to the slave device (14a-14n), and vice versa, and thus minimizes the possibility of read/write errors being encountered, while increasing the overall processing speed and efficiency of the system (1′).

    摘要翻译： 公开了一种用于启动具有主设备（1）和从设备（14a-14n）的系统（1'）的启动操作的方法和装置。 该方法包括以下步骤：A）使用主设备（1）来执行从设备（14a-14n）以确定需要设置电信号的时间关系以便操作系统（1'）的时间范围， 没有错误; B）将电信号的时间关系设置在所确定的时间范围内; 和C）存储所确定的时间范围的记录，以供随后在操作系统（1'）中使用。 在本发明的一个实施例中，系统（1'）包括计算机系统（1“）的存储器控​​制系统，并且从设备（14a-14n）包括计算机系统（1”）的存储设备。 本发明的方法基本上补偿从主设备（1）传送到从设备（14a-14n）的数据的到达时间的任何差异，反之亦然，从而使读/写错误的可能性最小化 同时提高系统的整体处理速度和效率（1'）。

    Dynamic line termination clamping circuit
    8.
    发明授权
    Dynamic line termination clamping circuit 失效
    动态线路终端钳位电路

    公开(公告)号：US6127840A

    公开(公告)日：2000-10-03

    申请号：US42912

    申请日：1998-03-17

    申请人： Paul William Coteus ,  Daniel Mark Dreps ,  Frank David Ferraiolo

    发明人： Paul William Coteus ,  Daniel Mark Dreps ,  Frank David Ferraiolo

    IPC分类号： H03K5/007 ,  H03K19/0175 ,  H04L25/02 ,  H03K17/16 ,  H03K19/003

    CPC分类号： H04L25/0278 ,  H04L25/028 ,  H04L25/0292

    摘要： A first circuit and a second circuit are connected by a pumped signal line that conducts a signal having a plurality of states. A dynamic termination circuit is connected to the pumped signal line. The dynamic termination circuit includes a switch responsive to the signal conducted by the pumped signal line such that the dynamic termination circuit is enabled only in response to certain of the plurality of states of the signal. In one embodiment, the switch is a first transistor that is coupled in series with a first impedance between a first reference voltage and an intermediate node. In this embodiment, the dynamic termination circuit further includes a second transistor coupled in series with a second impedance between a second reference voltage and the intermediate node and only first and second inverters that are each coupled between the intermediate node and the control input of a respective one of the first transistor and the second transistor.

    摘要翻译： 第一电路和第二电路通过导通具有多个状态的信号的泵浦信号线连接。 动态终端电路连接到泵浦信号线。 动态终端电路包括响应于由泵浦信号线传导的信号的开关，使得动态终端电路仅在响应于信号的多个状态中的某些状态时被使能。 在一个实施例中，开关是与第一参考电压和中间节点之间的第一阻抗串联耦合的第一晶体管。 在该实施例中，动态终端电路还包括与第二参考电压和中间节点之间的第二阻抗串联耦合的第二晶体管，并且仅包括第一和第二反相器，每个反相器耦合在相应的中间节点和控制输入端 第一晶体管和第二晶体管之一。

    Lead frame package for electronic devices
    9.
    发明授权
    Lead frame package for electronic devices 失效
    电子设备引线框架封装

    公开(公告)号：US5780925A

    公开(公告)日：1998-07-14

    申请号：US569561

    申请日：1995-12-08

    申请人： Thomas Mario Cipolla ,  Paul William Coteus

    发明人： Thomas Mario Cipolla ,  Paul William Coteus

    IPC分类号： H01L21/60 ,  H01L23/495 ,  H01L23/50 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    CPC分类号： H01L24/06 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107

    摘要： An electronic device packaging structure is described which contains a lead frame on which the electronic device is disposed. The electronic device has contact locations at one edge thereof. The lead frame has leads which extend under the electronic device and inwardly from the opposite direction. Wires are wire bonded between electronic device contact locations and the beam leads which extend under the electronic device and the ends of the leads which extend inwardly from the opposite direction. Two electronic devices are stacked in at an offset with respect to each to expose contact locations on the surface of each electronic device at an edge of each electronic device to form a stepped surface exposing a plurality of electronic device contact locations. Preferably, the chips are identical and rotated 180.degree. with respect to each other. Some of the leads of the lead frame for the double dense memory extend continuously under the stack to provide signal inputs through bit, address, control, power and ground inputs to the electronic devices. These inputs are common between the adjacent chips. Wires are bonded from contact locations on each chip to common leads. If a lead is common and cannot be mixed with another common lead, for example, a control line, it is located at the center of the lead frame. Other leads are provided which are not common between the two chips, for example chip select lines. Wires are bonded between the contact locations on each chip and at least one of the common leads of the lead frame.

    摘要翻译： 描述了一种电子设备包装结构，其包含设置电子设备的引线框架。 电子设备在其一个边缘处具有接触位置。 引线框架具有在电子设备下方延伸并且从相反方向向内延伸的引线。 导线在电子器件接触位置之间被引线接合，并且在电子器件下面延伸的光束引线和从相反方向向内延伸的引线的端部。 两个电子器件相对于每个电子器件以偏移方式堆叠以暴露每个电子器件的边缘处的每个电子器件的表面上的接触位置，以形成露出多个电子器件接触位置的台阶表面。 优选地，芯片相同并相对于彼此旋转180度。 双密度存储器的引线框架的一些引线在堆叠下连续延伸，以通过位，地址，控制，电源和接地输入向电子设备提供信号输入。 这些输入在相邻芯片之间是共同的。 电线从每个芯片上的接触位置连接到公共导线。 如果引线是常见的，并且不能与另一个公共引线（例如，控制线）混合，则它位于引线框架的中心。 提供了在两个芯片之间不常见的其它引线，例如芯片选择线。 电线结合在每个芯片上的接触位置和引线框架的至少一个公共引线之间。