公开(公告)号：US20110093644A1

公开(公告)日：2011-04-21

申请号：US12944660

申请日：2010-11-11

Applicant: Warren F. Kruger ,  Patrick Law ,  Alexander Miretsky

Inventor： Warren F. Kruger ,  Patrick Law ,  Alexander Miretsky

IPC: G06F13/00 ,  G06F13/14

CPC classification number: G06F13/1657

Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic.

Abstract translation: 描述了在单个集成电路设备上实现的分布式存储器控制器系统的实施例。 在一个实施例中，在第一多个存储器设备之间提供互连电路到第二多个存储器客户端的存储器控​​制器包括环形总线，用于在存储器客户机和存储器之间路由存储器请求和数据返回信号中的至少一个 设备。 环形总线被配置为分布在集成电路器件的一部分上的环形形状，导致存储器控制器中心处的最大布线密度的降低。 环形总线结构还减少了互连的总数以及存储元件的数量，从而减少了存储器控制器使用的总面积。 环形总线通过位于集成电路设备上的存储器件接口电路将物理上位于集成电路上的环形拓扑内的存储器客户端耦合到外部存储器件。 存储器控制器还包括使用环形总线上的虚拟通道用于一个或多个定义类型的总线业务的死锁避免机制。

公开(公告)号：US20080016254A1

公开(公告)日：2008-01-17

申请号：US11484191

申请日：2006-07-11

Applicant: Warren F. Kruger ,  Patrick Law ,  Alexander Miretsky

Inventor： Warren F. Kruger ,  Patrick Law ,  Alexander Miretsky

IPC: G06F15/16

CPC classification number: G06F13/1657

Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic

Abstract translation: 描述了在单个集成电路设备上实现的分布式存储器控制器系统的实施例。 在一个实施例中，在第一多个存储器设备之间提供互连电路到第二多个存储器客户端的存储器控​​制器包括环形总线，用于在存储器客户机和存储器之间路由存储器请求和数据返回信号中的至少一个 设备。 环形总线被配置为分布在集成电路器件的一部分上的环形形状，导致存储器控制器中心处的最大布线密度的降低。 环形总线结构还减少了互连的总数以及存储元件的数量，从而减少了存储器控制器使用的总面积。 环形总线通过位于集成电路设备上的存储器件接口电路将物理上位于集成电路上的环形拓扑内的存储器客户端耦合到外部存储器件。 存储器控制器还包括使用环形总线上的虚拟通道用于一个或多个定义类型的总线业务的死锁避免机制

公开(公告)号：US06647462B1

公开(公告)日：2003-11-11

申请号：US09607564

申请日：2000-06-29

Applicant: Alexander Miretsky ,  Vitaly Sukonik ,  Amit Dor ,  Rami Natan

Inventor： Alexander Miretsky ,  Vitaly Sukonik ,  Amit Dor ,  Rami Natan

IPC: G06F1200

CPC classification number: G06F9/3808 ,  G06F9/3802 ,  G06F12/0875

Abstract: An apparatus and a method for providing decoded information, the apparatus comprising: a memory module for storing encoded information; a decoder, coupled to the memory module, for fetching and decoding encoded information and for providing decoded information; and a cache, coupled to the memory module and to the decoder and to a recipient of decoded information, the cache is adapted to store at least one set of decoded information, to be provided to the recipient of information after a cache check condition is fulfilled and a cache hit occurs. A cache check condition is fulfilled when a change of flow occurs.

Abstract translation: 一种用于提供解码信息的装置和方法，所述装置包括：存储器模块，用于存储编码信息; 耦合到存储器模块的解码器，用于取得和解码经编码的信息并提供解码的信息; 以及高速缓存，其耦合到存储器模块，并且耦合到解码器和解码信息的接收者，高速缓存适于存储至少一组解码信息，以在高速缓存检查条件被满足之后提供给接收者信息 并发生缓存命中。 当发生流量变化时，满足缓存检查条件。

公开(公告)号：US07657774B1

公开(公告)日：2010-02-02

申请号：US12140144

申请日：2008-06-16

Applicant: Eric Hung ,  Geeta K. Desai ,  Vijendra Kuroodi ,  Alexander Miretsky ,  Mirko Vojnovic

Inventor： Eric Hung ,  Geeta K. Desai ,  Vijendra Kuroodi ,  Alexander Miretsky ,  Mirko Vojnovic

IPC: G06F1/00 ,  G06F1/04 ,  G06F12/00 ,  H05K1/00

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  Y02D10/126 ,  Y02D10/14

Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer. Thus, an overall electronic system is formed having a board with no more than two conductive layers, an execution engine that receives a first clock signal, a memory controller which receives a second clock signal, and a memory device that sends data to and from the memory controller at twice the rate of the second clock signal. Using a throttled second clock signal allows for less expensive packaging and mounting of packaged integrated circuits on a less expensive PCB, while still maintaining use of a DDR DRAM transfer mechanism.

Abstract translation: 提供了一种集成电路，其包括执行引擎和存储器控制器。 执行引擎以第一速率进行计时，并且存储器控制器以小于第一速率的第二速率被计时。 集成电路上的引脚可以以第二个时钟速率转换的第二个时钟的上升沿和下降沿将数据传输到集成电路和从集成电路传输数据。 集成电路优选地使用引线框封装，并且引线键从集成电路上的焊盘延伸到相应的引线。 引线固定到印刷电路板表面上的迹线导体上。 该电路板包含不超过两个由电介质层分离的导电层。 因此，整体电子系统形成为具有不超过两个导电层的板，接收第一时钟信号的执行引擎，接收第二时钟信号的存储器控​​制器以及向其发送数据的存储器件 存储器控制器是第二个时钟信号速率的两倍。 使用节流的第二时钟信号允许在廉价的PCB上封装和安装封装的集成电路，同时仍然保持使用DDR DRAM传输机制。

公开(公告)号：US06553487B1

公开(公告)日：2003-04-22

申请号：US09479200

申请日：2000-01-07

Applicant: Vitaly Sukonik ,  Alexander Miretsky ,  Amit Dor

Inventor： Vitaly Sukonik ,  Alexander Miretsky ,  Amit Dor

IPC: G06F944

CPC classification number: G06F9/462

Abstract: A device and method for performing high speed low overhead context switch, and especially in processors that handle multilevel nested tasks. The device handles forward requests and backward requests. The device is coupled to a central processing unit and has plurality of register files and a direct memory access mechanism that allows a processor to respond to a forward request by starting to handle a higher priority task using a first register file while transferring the halted task context from the second register file to a context save area within a memory module. The processor responds to a backward request by using the context that is stored in a first register file, while transferring to the second register file a lower priority task context.

Abstract translation: 一种用于执行高速低开销上下文切换的设备和方法，特别是在处理多层嵌套任务的处理器中。 设备处理转发请求和向后请求。 该设备耦合到中央处理单元并且具有多个寄存器文件和直接存储器访问机制，其允许处理器通过在传送停止的任务上下文的同时开始使用第一寄存器文件处理较高优先级任务来响应转发请求 从第二寄存器文件到存储器模块内的上下文保存区域。 处理器通过使用存储在第一寄存器文件中的上下文来响应反向请求，同时将较低优先级的任务上下文传送到第二寄存器文件。

公开(公告)号：US07849256B2

公开(公告)日：2010-12-07

申请号：US11484191

申请日：2006-07-11

Applicant: Warren F. Kruger ,  Patrick Law ,  Alexander Miretsky

Inventor： Warren F. Kruger ,  Patrick Law ,  Alexander Miretsky

IPC: G06F13/37

CPC classification number: G06F13/1657

Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.

Abstract translation: 描述了在单个集成电路设备上实现的分布式存储器控制器系统的实施例。 在一个实施例中，在第一多个存储器设备之间提供互连电路到第二多个存储器客户端的存储器控​​制器包括环形总线，用于在存储器客户机和存储器之间路由存储器请求和数据返回信号中的至少一个 设备。 环形总线被配置为分布在集成电路器件的一部分上的环形形状，导致存储器控制器中心处的最大布线密度的降低。 环形总线结构还减少了互连的总数以及存储元件的数量，从而减少了存储器控制器使用的总面积。

公开(公告)号：US07409572B1

公开(公告)日：2008-08-05

申请号：US10728492

申请日：2003-12-05

Applicant: Eric Hung ,  Geeta K. Desai ,  Vijendra Kuroodi ,  Alexander Miretsky ,  Mirko Vojnovic

Inventor： Eric Hung ,  Geeta K. Desai ,  Vijendra Kuroodi ,  Alexander Miretsky ,  Mirko Vojnovic

IPC: G06F1/00 ,  G06F1/04 ,  G06F1/12

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  Y02D10/126 ,  Y02D10/14

Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer. Thus, an overall electronic system is formed having a board with no more than two conductive layers, an execution engine that receives a first clock signal, a memory controller which receives a second clock signal, and a memory device that sends data to and from the memory controller at twice the rate of the second clock signal. Using a throttled second clock signal allows for less expensive packaging and mounting of packaged integrated circuits on a less expensive PCB, while still maintaining use of a DDR DRAM transfer mechanism.

Abstract translation: 提供了一种集成电路，其包括执行引擎和存储器控制器。 执行引擎以第一速率进行计时，并且存储器控制器以小于第一速率的第二速率被计时。 集成电路上的引脚可以以第二个时钟速率转换的第二个时钟的上升沿和下降沿将数据传输到集成电路和从集成电路传输数据。 集成电路优选地使用引线框封装，并且引线键从集成电路上的焊盘延伸到相应的引线。 引线固定到印刷电路板表面上的迹线导体上。 该电路板包含不超过两个由电介质层分离的导电层。 因此，整体电子系统形成为具有不超过两个导电层的板，接收第一时钟信号的执行引擎，接收第二时钟信号的存储器控​​制器以及向其发送数据的存储器件 存储器控制器是第二个时钟信号速率的两倍。 使用节流的第二时钟信号允许在廉价的PCB上封装和安装封装的集成电路，同时仍然保持使用DDR DRAM传输机制。