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    Apparatus and a method for providing decoded information
    3.
    发明授权
    Apparatus and a method for providing decoded information 失效
    装置和提供解码信息的方法

    公开(公告)号：US06647462B1

    公开(公告)日：2003-11-11

    申请号：US09607564

    申请日：2000-06-29

    申请人： Alexander Miretsky ,  Vitaly Sukonik ,  Amit Dor ,  Rami Natan

    发明人： Alexander Miretsky ,  Vitaly Sukonik ,  Amit Dor ,  Rami Natan

    IPC分类号： G06F1200

    CPC分类号： G06F9/3808 ,  G06F9/3802 ,  G06F12/0875

    摘要： An apparatus and a method for providing decoded information, the apparatus comprising: a memory module for storing encoded information; a decoder, coupled to the memory module, for fetching and decoding encoded information and for providing decoded information; and a cache, coupled to the memory module and to the decoder and to a recipient of decoded information, the cache is adapted to store at least one set of decoded information, to be provided to the recipient of information after a cache check condition is fulfilled and a cache hit occurs. A cache check condition is fulfilled when a change of flow occurs.

    摘要翻译： 一种用于提供解码信息的装置和方法，所述装置包括：存储器模块，用于存储编码信息; 耦合到存储器模块的解码器，用于取得和解码经编码的信息并提供解码的信息; 以及高速缓存，其耦合到存储器模块，并且耦合到解码器和解码信息的接收者，高速缓存适于存储至少一组解码信息，以在高速缓存检查条件被满足之后提供给接收者信息 并发生缓存命中。 当发生流量变化时，满足缓存检查条件。

    Programmable power transition counter
    5.
    发明申请
    Programmable power transition counter 有权

    公开(公告)号：US20060107077A1

    公开(公告)日：2006-05-18

    申请号：US10989948

    申请日：2004-11-15

    申请人： Charles Roth ,  Amit Dor

    发明人： Charles Roth ,  Amit Dor

    IPC分类号： G06F1/26

    CPC分类号： G06F9/30101 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D50/20

    摘要： Method, apparatus and system embodiments are disclosed for one or more programmable registers to hold wakeup time values for power management. For at least one embodiment, information based on the values in the programmable registers may be utilized by a power management unit to determine whether a power island has had sufficient time to transition out of a low power state. The values of the programmable registers may be dynamically modified during operation of a processing system. Other embodiments are also described and claimed.

    Frequency-dependent voltage control in digital logic
    6.
    发明申请
    Frequency-dependent voltage control in digital logic 有权
    数字逻辑中的频率依赖电压控制

    公开(公告)号：US20070006007A1

    公开(公告)日：2007-01-04

    申请号：US11173218

    申请日：2005-06-30

    申请人： Nancy Woodbridge ,  Mark Fullerton ,  Amit Dor ,  Vasudev Bibikar ,  Rajith Mavila

    发明人： Nancy Woodbridge ,  Mark Fullerton ,  Amit Dor ,  Vasudev Bibikar ,  Rajith Mavila

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.

    摘要翻译： 电子电路包括至少一个数字逻辑电路; 和电源控制电路。 功率控制电路可操作以响应于提供给至少一个数字逻辑电路的时钟频率的变化来调节提供给至少一个数字逻辑电路的功率信号的电压。 在另一实施例中，功率控制器可操作以在频率增加之前增加施加到数字逻辑电路的功率信号的电压，并且可操作地降低施加到数字逻辑电路之后的功率信号的电压 频率下降。

    Frequency-dependent voltage control in digital logic
    7.
    发明授权
    Frequency-dependent voltage control in digital logic 有权
    数字逻辑中的频率依赖电压控制

    公开(公告)号：US07603575B2

    公开(公告)日：2009-10-13

    申请号：US11173218

    申请日：2005-06-30

    申请人： Nancy G. Woodbridge ,  Mark N. Fullerton ,  Amit Dor ,  Vasudev Bibikar ,  Rajith Mavila

    发明人： Nancy G. Woodbridge ,  Mark N. Fullerton ,  Amit Dor ,  Vasudev Bibikar ,  Rajith Mavila

    IPC分类号： G06F1/00 ,  G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.

    摘要翻译： 电子电路包括至少一个数字逻辑电路; 和电源控制电路。 功率控制电路可操作以响应于提供给至少一个数字逻辑电路的时钟频率的变化来调节提供给至少一个数字逻辑电路的功率信号的电压。 在另一实施例中，功率控制器可操作以在频率增加之前增加施加到数字逻辑电路的功率信号的电压，并且可操作地降低施加到数字逻辑电路之后的功率信号的电压 频率下降。

    Programmable power transition counter
    8.
    发明授权
    Programmable power transition counter 有权
    可编程电源转换计数器

    公开(公告)号：US07529958B2

    公开(公告)日：2009-05-05

    申请号：US10989948

    申请日：2004-11-15

    申请人： Charles Roth ,  Amit Dor

    发明人： Charles Roth ,  Amit Dor

    IPC分类号： G06F1/00

    CPC分类号： G06F9/30101 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D50/20

    摘要： Method, apparatus and system embodiments are disclosed for one or more programmable registers to hold wakeup time values for power management. For at least one embodiment, information based on the values in the programmable registers may be utilized by a power management unit to determine whether a power island has had sufficient time to transition out of a low power state. The values of the programmable registers may be dynamically modified during operation of a processing system. Other embodiments are also described and claimed.

    摘要翻译： 公开了用于一个或多个可编程寄存器以保存用于电源管理的唤醒时间值的方法，装置和系统实施例。 对于至少一个实施例，基于可编程寄存器中的值的信息可以被电力管理单元利用以确定功率岛是否具有足够的时间来转换到低功率状态。 可编程寄存器的值可以在处理系统的操作期间动态修改。 还描述和要求保护其他实施例。

    Device and method for performing high-speed low overhead context switch
    10.
    发明授权
    Device and method for performing high-speed low overhead context switch 有权
    用于执行高速低开销上下文切换的设备和方法

    公开(公告)号：US06553487B1

    公开(公告)日：2003-04-22

    申请号：US09479200

    申请日：2000-01-07

    申请人： Vitaly Sukonik ,  Alexander Miretsky ,  Amit Dor

    发明人： Vitaly Sukonik ,  Alexander Miretsky ,  Amit Dor

    IPC分类号： G06F944

    CPC分类号： G06F9/462

    摘要： A device and method for performing high speed low overhead context switch, and especially in processors that handle multilevel nested tasks. The device handles forward requests and backward requests. The device is coupled to a central processing unit and has plurality of register files and a direct memory access mechanism that allows a processor to respond to a forward request by starting to handle a higher priority task using a first register file while transferring the halted task context from the second register file to a context save area within a memory module. The processor responds to a backward request by using the context that is stored in a first register file, while transferring to the second register file a lower priority task context.

    摘要翻译： 一种用于执行高速低开销上下文切换的设备和方法，特别是在处理多层嵌套任务的处理器中。 设备处理转发请求和向后请求。 该设备耦合到中央处理单元并且具有多个寄存器文件和直接存储器访问机制，其允许处理器通过在传送停止的任务上下文的同时开始使用第一寄存器文件处理较高优先级任务来响应转发请求 从第二寄存器文件到存储器模块内的上下文保存区域。 处理器通过使用存储在第一寄存器文件中的上下文来响应反向请求，同时将较低优先级的任务上下文传送到第二寄存器文件。