公开(公告)号：US20090245435A1

公开(公告)日：2009-10-01

申请号：US12413069

申请日：2009-03-27

申请人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

发明人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

IPC分类号： H04L27/06

CPC分类号： H04L1/0045 ,  H03M13/2957 ,  H03M13/6566 ,  H04L5/0007 ,  H04L27/2647

摘要： An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

摘要翻译： 描述了一种用于在移动通信系统中增强接收信道的下行链路处理的装置和方法，其包括用于控制数据和业务数据的缓冲器，具有至少两个独立操作的解映射器的解映射器引擎，用于对所述控制和业务数据进行解映射， 用于支持由解映射器引擎可访问的存储器段的似然比（LLR）缓冲器，包含解码器的解码器引擎，每个解码器对来自所选择的LLR缓冲器的所选存储器段的数据进行操作，以及至少提供至少控制的仲裁器 一个解映射引擎，LLR缓冲区和解码引擎。 解码器中的至少一个适合于解码控制数据，并且解码器中的另一个适合于解码业务数据。 通过分解解码，可以获得下行链路吞吐量的增加。

公开(公告)号：US08520571B2

公开(公告)日：2013-08-27

申请号：US12396270

申请日：2009-03-02

申请人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Ali RostamPisheh ,  Raghu Challa ,  Hemanth Sampath ,  Megan Wu ,  Joseph Zanotelli ,  Mrinal Nath

发明人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Ali RostamPisheh ,  Raghu Challa ,  Hemanth Sampath ,  Megan Wu ,  Joseph Zanotelli ,  Mrinal Nath

IPC分类号： H04B7/00

CPC分类号： G06F15/7842

摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

摘要翻译： 灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。 每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。 子电路的任务管理器可以配置和控制子电路的可配置硬件。 中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。 每个任务列表包括相应子电路的任务指令。 子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。 时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

公开(公告)号：US08572332B2

公开(公告)日：2013-10-29

申请号：US12404613

申请日：2009-03-16

申请人： Ali RostamPisheh ,  Raghu N. Challa ,  Iwen Yao ,  Davie J. Santos ,  Mrinal M. Nath

发明人： Ali RostamPisheh ,  Raghu N. Challa ,  Iwen Yao ,  Davie J. Santos ,  Mrinal M. Nath

IPC分类号： G06F12/00

CPC分类号： H03M13/2785 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2775 ,  H03M13/6566

摘要： A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.

摘要翻译： 解交织器产生多个解交织重排物理（DRP）地址，以将对应的多个LLR值同时写入多存储存储器，使得不多于一个LLR值被写入多存储体的每个存储体 一次记忆 这种并行写入的序列导致存储在存储器中的子包的传输的LLR值。 在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体中，使得解码器可以以解交织的顺序读出存储器中的LLR值。 存储体的每个存储器位置是用于存储多个相关LLR值的字位置，其中一个LLR值与其奇偶校验值一起存储。 用于同时写入多个LLR值的能力用于以快速有效的方式清除位置。

公开(公告)号：US20090245423A1

公开(公告)日：2009-10-01

申请号：US12333131

申请日：2008-12-11

申请人： Ali RostamPisheh ,  Raghu Challa ,  Ravi Palanki

发明人： Ali RostamPisheh ,  Raghu Challa ,  Ravi Palanki

IPC分类号： H04L27/00 ,  G06F12/00

CPC分类号： H04L27/2647 ,  H03M13/2757 ,  H03M13/276 ,  H03M13/2764 ,  H03M13/2789 ,  H04L1/0052 ,  H04L1/0071

摘要： A de-interleaver involves logic that receives a seed and that simultaneously generates from the seed a plurality of reorder indices. The plurality of reorder indices is usable for de-interleaving an incoming stream of interleaved code bits. Each plurality of simultaneously generated reorder indices generated corresponds to a set of simultaneously received code bits in the incoming stream. The reorder indices are converted into physical addresses in parallel and these physical addresses are used to store the set of code bits into a memory. Code bits for multiple sub-packets of different sub-packet sizes are typically present in memory at the same time. The code bits are then read out of memory to form an outgoing stream of de-interleaved code bits. The de-interleaver has a pipelined architecture such that sets of code bits are written into the memory at the same rate that sets of code bits are received onto the de-interleaver.

摘要翻译： 解交织器涉及接收种子并且同时从种子生成多个重排序索引的逻辑。 多个重排序索引可用于对交错码位的输入流进行解交织。 生成的每个多个同时生成的再排序索引对应于输入流中的一组同时接收的码位。 重排序索引并行转换为物理地址，这些物理地址用于将码位集合存储到存储器中。 不同子包大小的多个子包的码位通常同时存在于存储器中。 然后，代码位从存储器中读出以形成去交错码位的输出流。 解交织器具有流水线架构，使得将码组集合以相同的速率写入存储器中，使得码位组被接收到解交织器上。

公开(公告)号：US08576955B2

公开(公告)日：2013-11-05

申请号：US12413069

申请日：2009-03-27

申请人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

发明人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

IPC分类号： H04L27/06

CPC分类号： H04L1/0045 ,  H03M13/2957 ,  H03M13/6566 ,  H04L5/0007 ,  H04L27/2647

摘要： An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

摘要翻译： 描述了一种用于在移动通信系统中增强接收信道的下行链路处理的装置和方法，其包括用于控制数据和业务数据的缓冲器，具有至少两个独立操作的解映射器的解映射器引擎，用于对所述控制和业务数据进行解映射， 用于支持由解映射器引擎可访问的存储器段的似然比（LLR）缓冲器，包含解码器的解码器引擎，每个解码器对来自所选择的LLR缓冲器的所选存储器段的数据进行操作，以及至少提供至少控制的仲裁器 一个解映射引擎，LLR缓冲区和解码引擎。 解码器中的至少一个适合于解码控制数据，并且解码器中的另一个适合于解码业务数据。 通过分解解码，可以获得下行链路吞吐量的增加。

公开(公告)号：US20090249134A1

公开(公告)日：2009-10-01

申请号：US12404613

申请日：2009-03-16

申请人： Ali RostamPisheh ,  Raghu N. Challa ,  Iwen Yao ,  Davie J. Santos ,  Mrinal M. Nath

发明人： Ali RostamPisheh ,  Raghu N. Challa ,  Iwen Yao ,  Davie J. Santos ,  Mrinal M. Nath

IPC分类号： G11C29/00 ,  G06F12/02

CPC分类号： H03M13/2785 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2775 ,  H03M13/6566

摘要： A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.

摘要翻译： 解交织器生成多个解交织重排物理（DRP）地址，以将对应的多个LLR值同时写入多存储存储器，使得不多于一个LLR值被写入多存储体的每个存储体 一次记忆 这种并行写入的序列导致存储在存储器中的子包的传输的LLR值。 在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体中，使得解码器可以以解交织的顺序读出存储器中的LLR值。 存储体的每个存储器位置是用于存储多个相关LLR值的字位置，其中一个LLR值与其奇偶校验值一起存储。 用于同时写入多个LLR值的能力用于以快速有效的方式清除位置。

公开(公告)号：US20090245192A1

公开(公告)日：2009-10-01

申请号：US12396270

申请日：2009-03-02

申请人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Ali Rostampisheh ,  Raghu Challa ,  Hamanth Sampath ,  Min Wu ,  Joseph Zanotelli ,  Mrinal M. Nath

发明人： Arunava Chaudhuri ,  Iwen Yao ,  Jeremy H. Lin ,  Ali Rostampisheh ,  Raghu Challa ,  Hamanth Sampath ,  Min Wu ,  Joseph Zanotelli ,  Mrinal M. Nath

IPC分类号： H04W88/16 ,  G06F9/46

CPC分类号： G06F15/7842

摘要： A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

摘要翻译： 灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。 每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。 子电路的任务管理器可以配置和控制子电路的可配置硬件。 中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。 每个任务列表包括相应子电路的任务指令。 子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。 时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。