公开(公告)号：US20050122331A1

公开(公告)日：2005-06-09

申请号：US10987120

申请日：2004-11-12

申请人： Charles Boyd ,  Michele Boland ,  Michael Toelle ,  Anantha Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen Wright

发明人： Charles Boyd ,  Michele Boland ,  Michael Toelle ,  Anantha Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen Wright

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F13/14 ,  G06F15/00 ,  G06T1/00 ,  G06T15/00

CPC分类号： G06F9/325 ,  G06F9/3842 ,  G06F9/3879 ,  G06T15/005 ,  G06T15/80

摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

公开(公告)号：US20070035752A1

公开(公告)日：2007-02-15

申请号：US11203740

申请日：2005-08-15

申请人： Glenn Evans ,  Benjamin Ellett ,  David Blythe ,  Anantha Kancherla ,  Bradley Gibson ,  Michael Stokes ,  Steven White ,  Denis Demandolx

发明人： Glenn Evans ,  Benjamin Ellett ,  David Blythe ,  Anantha Kancherla ,  Bradley Gibson ,  Michael Stokes ,  Steven White ,  Denis Demandolx

IPC分类号： H04N1/60

CPC分类号： H04N1/603

摘要： Methods for mapping color data having at least one color associated therewith to an output device based on an input device profile and an output device profile, each profile having a tone curve and a color matrix, are provided. In one embodiment, the method includes receiving color data from an input device and determining whether the color data is in a linear space. If it is determined that the color data is not in a linear space, the method further includes applying the tone curve of the input device profile to the color data to convert it into a linear space. The method further includes converting the color(s) associated with the color data from the input linear space to an output linear space by applying the color matrix of the input device profile and the inverse color matrix of the output device profile to create color-converted image data.

摘要翻译： 提供了基于输入设备配置文件和输出设备配置文件将具有与其相关联的至少一种颜色的颜色数据映射到输出设备的方法，每个配置文件具有色调曲线和颜色矩阵。 在一个实施例中，该方法包括从输入装置接收彩色数据并确定彩色数据是否处于线性空间。 如果确定颜色数据不在线性空间中，则该方法还包括将输入设备简档的色调曲线应用于颜色数据以将其转换为线性空间。 该方法还包括通过应用输出设备配置文件的颜色矩阵和输出设备配置文件的反色矩阵来将与输入线性空间的颜色数据相关联的颜色转换为输出线性空间，以创建颜色转换 图像数据。

公开(公告)号：US20050122332A1

公开(公告)日：2005-06-09

申请号：US10987144

申请日：2004-11-12

申请人： Charles Boyd ,  Michele Boland ,  Michael Toelle ,  Anantha Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen Wright

发明人： Charles Boyd ,  Michele Boland ,  Michael Toelle ,  Anantha Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen Wright

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F13/14 ,  G06F15/00 ,  G06T1/00 ,  G06T15/00

CPC分类号： G06F9/325 ,  G06F9/3842 ,  G06F9/3879 ,  G06T15/005 ,  G06T15/80

摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

公开(公告)号：US20050122334A1

公开(公告)日：2005-06-09

申请号：US10987686

申请日：2004-11-12

申请人： Charles Boyd ,  Michele Boland ,  Michael Toelle ,  Anantha Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen Wright

发明人： Charles Boyd ,  Michele Boland ,  Michael Toelle ,  Anantha Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen Wright

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F13/14 ,  G06F15/00 ,  G06T1/00 ,  G06T15/00

CPC分类号： G06F9/325 ,  G06F9/3842 ,  G06F9/3879 ,  G06T15/005 ,  G06T15/80

摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

公开(公告)号：US20050122330A1

公开(公告)日：2005-06-09

申请号：US10986586

申请日：2004-11-12

申请人： Charles Boyd ,  Michele Boland ,  Michael Toelle ,  Anantha Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen Wright

发明人： Charles Boyd ,  Michele Boland ,  Michael Toelle ,  Anantha Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen Wright

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F13/14 ,  G06F15/00 ,  G06T1/00 ,  G06T15/00

CPC分类号： G06F9/325 ,  G06F9/3842 ,  G06F9/3879 ,  G06T15/005 ,  G06T15/80

摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.