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1.发明申请Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques 有权将算法元素下载到协处理器的系统和方法以及相应的技术公开(公告)号：US20050122332A1
公开(公告)日：2005-06-09
申请号：US10987144
申请日：2004-11-12
申请人： Charles Boyd , Michele Boland , Michael Toelle , Anantha Kancherla , Amar Patel , Iouri Tarassov , Stephen Wright
发明人： Charles Boyd , Michele Boland , Michael Toelle , Anantha Kancherla , Amar Patel , Iouri Tarassov , Stephen Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流程控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。
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公开(公告)号：US20050122334A1
公开(公告)日：2005-06-09
申请号：US10987686
申请日：2004-11-12
申请人： Charles Boyd , Michele Boland , Michael Toelle , Anantha Kancherla , Amar Patel , Iouri Tarassov , Stephen Wright
发明人： Charles Boyd , Michele Boland , Michael Toelle , Anantha Kancherla , Amar Patel , Iouri Tarassov , Stephen Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
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公开(公告)号：US20050122330A1
公开(公告)日：2005-06-09
申请号：US10986586
申请日：2004-11-12
申请人： Charles Boyd , Michele Boland , Michael Toelle , Anantha Kancherla , Amar Patel , Iouri Tarassov , Stephen Wright
发明人： Charles Boyd , Michele Boland , Michael Toelle , Anantha Kancherla , Amar Patel , Iouri Tarassov , Stephen Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
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公开(公告)号：US20050122331A1
公开(公告)日：2005-06-09
申请号：US10987120
申请日：2004-11-12
申请人： Charles Boyd , Michele Boland , Michael Toelle , Anantha Kancherla , Amar Patel , Iouri Tarassov , Stephen Wright
发明人： Charles Boyd , Michele Boland , Michael Toelle , Anantha Kancherla , Amar Patel , Iouri Tarassov , Stephen Wright
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3879 , G06T15/005 , G06T15/80
摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.
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公开(公告)号：US20050243094A1
公开(公告)日：2005-11-03
申请号：US10934249
申请日：2004-09-03
申请人： Amar Patel , Charles Boyd , David Blythe , Jeff Noyle , Michael Toelle , Stephen Wright
发明人： Amar Patel , Charles Boyd , David Blythe , Jeff Noyle , Michael Toelle , Stephen Wright
CPC分类号： G06T15/005
摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.
摘要翻译： 提供了增强的图形流水线，其使公共核心硬件能够执行图形流水线的不同组件，由流水线中的组件包括线和三角形的原语的可编程性，以及在呈现与图形显示之间的流输出 数据在管道中。 编程人员不必优化代码，因为通用核心将平衡所需功能的负载，并在通用核心硬件上动态分配这些指令。 程序员可以使用算法编程原语，以通过用线和三角形进行拓扑替换来简化所有顶点计算。 程序员获取计算的输出数据，并在渲染之前或期间读取它们。 因此，程序员在编程中具有更大的灵活性。 通过使用增强型图形管线，程序员可以优化管道中硬件的使用，程序顶点，线或三角形拓扑，而不是单独使用每个顶点，并从管道可以输出计算的信息的内存读取任何计算的数据。
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公开(公告)号：US20050140669A1
公开(公告)日：2005-06-30
申请号：US10981963
申请日：2004-11-05
申请人： Charles Boyd , Michael Toelle
发明人： Charles Boyd , Michael Toelle
CPC分类号： G06T15/00 , G06T15/005 , G06T15/80 , G06T2210/32
摘要： A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.
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7.发明申请公开(公告)号：US20050086317A1
公开(公告)日：2005-04-21
申请号：US10971450
申请日：2004-10-22
申请人： Charles Boyd , Michael Toelle
发明人： Charles Boyd , Michael Toelle
CPC分类号： G06T15/005
摘要： An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.
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公开(公告)号：US20050030312A1
公开(公告)日：2005-02-10
申请号：US10937031
申请日：2004-09-09
申请人： Charles Boyd , Michael Toelle
发明人： Charles Boyd , Michael Toelle
CPC分类号： G06T15/00 , G06T15/005 , G06T15/80 , G06T2210/32
摘要： A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.
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公开(公告)号：US20060125823A1
公开(公告)日：2006-06-15
申请号：US11346897
申请日：2006-02-03
申请人： Charles Boyd , Michael Toelle
发明人： Charles Boyd , Michael Toelle
IPC分类号： G06T15/00
CPC分类号： G06T1/60
摘要： An API is provided to feed multiple data objects, wherever originated or located at the time of operation, to a 3D graphics chip simultaneously or in parallel. Multiple containers may be fed to a 3D graphics chip memory at the same time. In the case where data is being transmitted to a graphics chip memory, wherein the data includes the same spatial position of pixel(s), but only the orientation or color is changing, the data may be loaded into two separate containers, with a header description understood by the graphics chip and implemented by the graphics API, whereby a single copy of the position data can be loaded into one container, and the changing color or orientation data may be loaded into a second container. Thus, when received by the graphics chip, the data is loaded correctly into register space and processed according to the header description.
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10.发明申请Method and system for defining and controlling algorithmic elements in a graphics display system 有权用于在图形显示系统中定义和控制算法元素的方法和系统公开(公告)号：US20050086669A1
公开(公告)日：2005-04-21
申请号：US10971248
申请日：2004-10-22
申请人： Charles Boyd , Michael Toelle
发明人： Charles Boyd , Michael Toelle
CPC分类号： G06T15/005
摘要： An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.
摘要翻译： 提供了一种能够实现3D芯片的可编程性的API，其中由开发者编写的编程或算法元素可以被下载到芯片，从而对芯片进行编程以执行这些算法。 开发人员将可下载的例程写入3D图形芯片。 还提供了一组与已经为开发人员编程的API相关联的算法元素，可以下载到可编程芯片以提高性能。 因此，开发人员可以将预先存在的API对象下载到3D图形芯片。 开发人员坚持使用特定格式来打包一个由3D图形芯片实现的算法元素或指令集。 开发人员通过参考3D图形芯片了解的“令牌”列表将指令集打包成数组。 这个数组依次被正确地映射到3D图形芯片，用于由3D图形芯片实现算法元素。
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