公开(公告)号：US06169453A

公开(公告)日：2001-01-02

申请号：US09314048

申请日：1999-05-18

申请人： Andrea Milanesi ,  Vanni Poletto

发明人： Andrea Milanesi ,  Vanni Poletto

IPC分类号： H03F345

CPC分类号： H03F3/45479

摘要： A differential amplifier provides a high common mode rejection while maintaining substantially unchanged the input dynamic range. The differential amplifier includes a comparator having inputs to which are applied the two input signals, which are also applied to an operational amplifier, so that the comparator outputs a signal whose sign is indicative of the sign of the difference between the two input signals. The output of the operational amplifier is feedback to one of the inputs of the operational amplifier through a current mirror. This feedback signal is switched between the non-inverting input of the operational amplifier and the inverting input of the operational amplifier. The switching of the feedback signal ensures negative feedback, and is dependent upon the sign of the difference detected by the comparator.

摘要翻译： 差分放大器提供高共模抑制，同时保持输入动态范围基本不变。 差分放大器包括具有输入的比较器，对其施加也被施加到运算放大器的两个输入信号，使得比较器输出其符号表示两个输入信号之间的差的符号的信号。 运算放大器的输出通过电流镜反馈到运算放大器的一个输入端。 该反馈信号在运算放大器的非反相输入和运算放大器的反相输入之间切换。 反馈信号的切换确保负反馈，并且取决于比较器检测到的差异的符号。

公开(公告)号：US6040736A

公开(公告)日：2000-03-21

申请号：US984959

申请日：1997-12-04

申请人： Andrea Milanesi ,  Vanni Poletto ,  Alberto Poma ,  Marco Morelli

发明人： Andrea Milanesi ,  Vanni Poletto ,  Alberto Poma ,  Marco Morelli

IPC分类号： G05F1/575 ,  G05F1/10

CPC分类号： G05F1/575

摘要： A voltage-regulator circuit with a low voltage drop uses a DMOS power transistor driven by a charge pump. The control circuit includes two feedback loops: a first feedback loop having a high gain and accuracy but low response speed, and a second feedback loop having a wide passband and fast response speed, but low gain.

摘要翻译： 具有低压降的电压调节器电路使用由电荷泵驱动的DMOS功率晶体管。 控制电路包括两个反馈回路：具有高增益和精度但低响应速度的第一反馈回路，以及具有宽通带和快速响应速度但低增益的第二反馈回路。

公开(公告)号：US06762643B2

公开(公告)日：2004-07-13

申请号：US10297730

申请日：2002-12-06

申请人： Andrea Milanesi

发明人： Andrea Milanesi

IPC分类号： H03F102

CPC分类号： H03F3/45977 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45753

摘要： A circuit arrangement comprising an input amplifier stage (31) with two inputs (36, 37) and an output (34) being connectable to an input (35) of an output amplifier stage (32). The circuit furthermore comprises a comparator (33) with a first input (41), a second input (42) and a comparator output (44), a feedback capacitor (43) connected to an offset tuning input (45) of the input amplifier stage (31), and a plurality of switches (S1, S2) that are controllable by switching signals (V1, V2) to allow the circuit to be switched from a first phase to a second phase. During the first phase (1), the output (34) and the input (35) are separated by a first one of the switches (S2) and the two inputs (36, 37) are connected via a second one of the switches (S1). The first input (41) of the comparator (33) is connected to the output (34) of the input amplifier stage (31) and the second input (42) of the comparator (33) is connected to the input (35) of the output amplifier stage (32) such that via the comparator output (44) a charge on the feedback capacitor (43), and hence the voltage at the offset tuning input (45) is altered and an offset of the input amplifier stage (31) is corrected.

摘要翻译： 一种电路装置，包括具有两个输入端（36,37）的输入放大器级（31）和可连接到输出放大器级（32）的输入端（35）的输出端（34）。 电路还包括具有第一输入（41），第二输入（42）和比较器输出（44）的比较器（33），连接到输入放大器的偏移调谐输入（45）的反馈电容器（43） 阶段（31）和多个开关（S1，S2），其可由开关信号（V1，V2）控制，以允许电路从第一相切换到第二相。 在第一阶段（1）期间，输出（34）和输入（35）由第一个开关（S2）分开，两个输入端（36,37）经由第二个开关（ S1）。 比较器（33）的第一输入端（41）连接到输入放大级（31）的输出端（34），比较器（33）的第二输入端（42）连接到 输出放大器级（32）使得经由比较器输出（44）反馈电容器（43）上的电荷以及偏移调谐输入（45）上的电压被改变，并且输入放大器级（31）的偏移 ）被修正。

公开(公告)号：US06437607B1

公开(公告)日：2002-08-20

申请号：US09697234

申请日：2000-10-26

申请人： Andrea Milanesi

发明人： Andrea Milanesi

IPC分类号： H03K522

CPC分类号： G01R19/16528 ,  G01R19/16571

摘要： Non linear circuit for open load control in Low-Side Driver type circuits, including at least two power transistors, scaled according to an area ratio 1 to M, with M>1, wherein the power transistor having the smaller area is controlled by a circuit input signal while the transistor having the larger area is controlled by an output value of an AND type logic gate, managed by a control circuit, that is regulated by the output value of a voltage sensor, placed in parallel with the power transistor having the larger area, and by the output value of a current sensor, placed in series with the power transistor having the smaller area, so that, when a current flowing in the power transistor having the smaller area is less than a predetermined value of the threshold current, the control circuit signals the open load on an output pin.

摘要翻译： 用于低侧驱动器类型电路中的开路负载控制的非线性电路，包括至少两个功率晶体管，按照M> 1的面积比1至M来缩放，其中具有较小面积的功率晶体管由电路 输入信号，而具有较大面积的晶体管由AND型逻辑门的输出值控制，该输出值由控制电路管理，该输出值由电压传感器的输出值调节，与具有较大面积的功率晶体管并联放置 以及与具有较小面积的功率晶体管串联布置的电流传感器的输出值，使得当流过具有较小面积的功率晶体管的电流小于阈值电流的预定值时， 控制电路用信号通知输出引脚上的开路负载。

公开(公告)号：US20060279509A1

公开(公告)日：2006-12-14

申请号：US10563995

申请日：2004-06-30

申请人： Andrea Milanesi

发明人： Andrea Milanesi

IPC分类号： G09G3/36

CPC分类号： H03F3/45744 ,  H03F3/4521 ,  H03F3/45219 ,  H03F2200/375 ,  H03F2203/45616

摘要： Apparatus (80) comprising an input stage (61) with an NMOS transistor doublet having a first differential input for receiving input signals, and a PMOS transistor doublet having a second differential input for receiving input signals. The apparatus (80) further comprises switching means for receiving and selectively directing analog input signals either to the first differential input or to the second differential input. The means are controlled by a switching signal ((,p in a manner to keep the ratio of the transconductance of the NMOS transistor doublet and the transconductance of the PMOS transistor doublet constant.

摘要翻译： 装置（80）包括具有NMOS晶体管双极的输入级（61），具有用于接收输入信号的第一差分输入和具有用于接收输入信号的第二差分输入的PMOS晶体管双极。 装置（80）还包括用于接收并选择性地将模拟输入信号定向到第一差分输入或第二差分输入的切换装置。 该装置由开关信号（（，p，以保持NMOS晶体管的跨导的比例和PMOS晶体管的跨导双重恒定）的方式控制。

公开(公告)号：US6049244A

公开(公告)日：2000-04-11

申请号：US63419

申请日：1998-04-20

申请人： Andrea Milanesi

发明人： Andrea Milanesi

IPC分类号： H01L31/00

CPC分类号： G05F3/242

摘要： A circuit for the generation of an electrical signal of constant duration comprises a capacitor, a constant current generator for charging the capacitor, and a voltage comparator to compare the voltage present at the terminals of the capacitor with a reference voltage. The voltage comparator supplies at an output a digital signal dependent upon the voltage across the capacitor. The constant current generator comprises a transistor biased with a voltage between gate and source obtained as the difference between the sum of two gate-source voltages of two transistors and a gate-source voltage of another transistor.

摘要翻译： 用于产生恒定持续时间的电信号的电路包括电容器，用于对电容器充电的恒定电流发生器和用于将存在于电容器的端子处的电压与参考电压进行比较的电压比较器。 电压比较器根据电容器两端的电压在输出端提供数字信号。 恒流发生器包括以栅极和源极之间的电压偏置的晶体管，其被获得为两个晶体管的两个栅极 - 源极电压之和和另一个晶体管的栅极 - 源极电压之差。

公开(公告)号：US08022945B2

公开(公告)日：2011-09-20

申请号：US10563995

申请日：2004-06-30

申请人： Andrea Milanesi

发明人： Andrea Milanesi

IPC分类号： G06F3/038

CPC分类号： H03F3/45744 ,  H03F3/4521 ,  H03F3/45219 ,  H03F2200/375 ,  H03F2203/45616

摘要： Apparatus (80) comprising an input stage (61) with an NMOS transistor doublet having a first differential input for receiving input signals, and a PMOS transistor doublet having a second differential input for receiving input signals. The apparatus (80) further comprises switching means for receiving and selectively directing analog input signals either to the first differential input or to the second differential input. The means are controlled by a switching signal (φ,φ) in a manner to keep the ratio of the transconductance of the NMOS transistor doublet and the transconductance of the PMOS transistor doublet constant.

摘要翻译： 装置（80）包括具有NMOS晶体管双极的输入级（61），具有用于接收输入信号的第一差分输入和具有用于接收输入信号的第二差分输入的PMOS晶体管双极。 装置（80）还包括用于接收并选择性地将模拟输入信号定向到第一差分输入或第二差分输入的切换装置。 该装置以保持NMOS晶体管的跨导比和PMOS晶体管的跨导倍数恒定的方式由开关信号（＆phgr。，＆phgr。）控制。

公开(公告)号：US06483085B1

公开(公告)日：2002-11-19

申请号：US09712412

申请日：2000-11-13

申请人： Andrea Milanesi ,  Vanni Poletto ,  Paolo Ghigini

发明人： Andrea Milanesi ,  Vanni Poletto ,  Paolo Ghigini

IPC分类号： H05B102

CPC分类号： G05D23/2401

摘要： A temperature control system and method for integrated circuits, particularly those having a plurality of channels or power devices. The temperature control system for an integrated circuit includes at least a heat generating device; a sensor element providing a signal correlated to the working conditions of said the heat generating device such as a signal proportional to the dissipated power of the heat generating device; an elaboration circuit of the signal correlated to the working conditions of the heat generating device; and a turning off circuit of said at least a heat generating device responsively to a signal of said elaboration circuit.

摘要翻译： 一种用于集成电路的温度控制系统和方法，特别是具有多个通道或功率器件的那些。 集成电路的温度控制系统至少包括发热装置; 提供与所述发热装置的工作条件相关的信号的传感器元件，例如与发热装置的耗散功率成比例的信号; 该信号的精密电路与发热装置的工作条件相关; 以及响应于所述精细电路的信号的所述至少一个发热装置的关闭电路。

公开(公告)号：US06462557B1

公开(公告)日：2002-10-08

申请号：US09570874

申请日：2000-05-15

申请人： Andrea Milanesi ,  Stefania Chicca ,  Vanni Poletto ,  Valerio Giorgetta ,  Stefano Sgatti ,  Sergio Vigna

发明人： Andrea Milanesi ,  Stefania Chicca ,  Vanni Poletto ,  Valerio Giorgetta ,  Stefano Sgatti ,  Sergio Vigna

IPC分类号： G08B2100

CPC分类号： G01R31/024

摘要： A system for diagnosing a driver and detecting circuit anomalies therein includes: voltage comparator circuits for generating diagnostic logic signals, each of which indicates the existence of a corresponding type of anomaly; and a coding circuit to receive the diagnostic logic signals and to output information relating to an overall operating state of the driver. The coding circuit includes a first portion to provide at its output first logic input signals indicating the last anomaly to occur since a system reset operation. The coding circuit also includes a second portion for coding the first logic input signals. The second portion includes a sequential logic network to receive the first logic input signals and at least one second logic signal indicating the current operating phase of the driver. The second portion provides, as a function of the first and second logic signals, a stable internal state to determine the output information in the form of an N bit coded word. The N bit coded word is representative of the occurrence of an anomaly, of an absence of an anomaly in the current operating phase, or of an absence of an anomaly in any operating phase.

摘要翻译： 用于诊断驱动器并检测电路异常的系统包括：用于产生诊断逻辑信号的电压比较器电路，每个诊断逻辑信号指示存在相应类型的异常; 以及编码电路，用于接收诊断逻辑信号并输出​​与驾驶员的总体操作状态有关的信息。 编码电路包括第一部分，在其输出端提供第一逻辑输入信号，指示自系统复位操作以来发生的最后一个异常。 编码电路还包括用于对第一逻辑输入信号进行编码的第二部分。 第二部分包括用于接收第一逻辑输入信号的顺序逻辑网络和指示驾驶员的当前操作阶段的至少一个第二逻辑信号。 第二部分提供作为第一和第二逻辑信号的函数的稳定的内部状态，以以N位编码字的形式确定输出信息。 N位编码字表示在当前操作阶段中不存在异常或者在任何操作阶段中不存在异常的异常的发生。

公开(公告)号：US06292341B1

公开(公告)日：2001-09-18

申请号：US09295842

申请日：1999-04-21

申请人： Andrea Milanesi ,  Stefania Chicca ,  Marco Morelli ,  Vanni Poletto

发明人： Andrea Milanesi ,  Stefania Chicca ,  Marco Morelli ,  Vanni Poletto

IPC分类号： H02H318

CPC分类号： H03K17/0822

摘要： A protection circuit of a diagnostic output line (K-line) of a control unit for protection of the control unit in the event of a ground disconnection or of a “below ground” condition is provided. The diagnostic output line includes a first interface DMOS transistor with a source connected to ground and a drain coupled to the diagnostic output line through a second DMOS transistor with a source connected to the output line and a drain connected to the source of the first DMOS transistor. The protection circuit also includes a comparator for the voltage of the diagnostic output line with the potential of the ground node, and a two-input logic gate, whose output controls a current generator forcing a current, limited by a resistor, on the diagnostic output line.

摘要翻译： 提供用于在接地断开或“低于地面”情况下保护控制单元的控制单元的诊断输出线（K线）的保护电路。 诊断输出线包括具有源极连接到地的第一接口DMOS晶体管和通过连接到输出线的源极的第二DMOS晶体管耦合到诊断输出线的漏极，以及连接到第一DMOS晶体管的源极的漏极 。 保护电路还包括用于具有接地节点的电位的诊断输出线的电压的比较器，以及双输入逻辑门，其输出控制电流发生器强制由电阻器限制的电流在诊断输出端 线。