Method and implement for load securement

    公开(公告)号:US11752922B1

    公开(公告)日:2023-09-12

    申请号:US16930636

    申请日:2020-07-16

    摘要: A load securement device may comprise an extendable pole and a plurality of attachments. The device may be operable to manipulate a tie down of a cargo trailer. As non-limiting examples, the tie down may be a cargo strap, a cargo chain, or an elastic cord used to secure a cargo or to secure a tarp over the cargo. The extendable pole may be lengthened to reach the top of the cargo. The extendable pole may be shortened to take up less space for storage. The plurality of attachments may alter a distal end of the extendable pole to enable the extendable pole to perform multiple tasks necessary for securing the cargo. As non-limiting examples, the plurality of attachments may enable the extendable pole to toss the cargo strap, to pull the cargo strap, or lift a hard corner.

    Partial mismatch-shaping digital-to-analog converter
    2.
    发明授权
    Partial mismatch-shaping digital-to-analog converter 有权
    部分失配整形数模转换器

    公开(公告)号:US06697004B1

    公开(公告)日:2004-02-24

    申请号:US09969206

    申请日:2001-10-01

    IPC分类号: H03M166

    摘要: A novel mismatched-shaping DAC architecture is described. The inventive DAC partially spectrally shapes data conversion errors. In accordance with the present invention, the DAC mismatch-shaping function is fully effective for input signal amplitude levels that are relatively low (i.e., close to mid-scale), however, the mismatch-shaping function is not fully effective for input signal amplitude levels that are relatively high. This results in the simplification in complexity, reduced power dissipation, and shortened propagation delays associated with the mismatch-shaping DAC digital logic circuitry. Exemplary delta-sigma ADC and DAC architectures adapted for use with the present inventive partial mismatch-shaping DAC are also described.

    摘要翻译: 描述了一种新颖的失配整形DAC体系结构。 本发明的DAC部分地光谱地形成数据转换误差。 根据本发明,DAC失配整形功能对于相对较低(即,接近中等尺度)的输入信号幅度电平是完全有效的,然而,失配整形功能对于输入信号幅度不是完全有效 水平相对较高。 这导致复杂度的简化,降低的功率耗散以及与失配整形DAC数字逻辑电路相关联的缩短的传播延迟。 还描述了适用于本发明的部分失配整形DAC的示例性Δ-ΣADC和DAC架构。