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公开(公告)号：US12056055B2
公开(公告)日：2024-08-06
申请号：US17619760
申请日：2021-04-28
发明人： Xuyan Ma , Jianhua Wu , Shaoli Liu , Xiangxuan Ge , Hanbo Liu , Lei Zhang
IPC分类号： G06F12/0877
CPC分类号： G06F12/0877 , G06F2212/1016
摘要： A data processing device and related products are provided. The data processing device includes: a decoding unit, a discrete address determining unit, a continuous data caching unit, a data read/write unit, and a storage unit. Through the data processing device, the processing instruction may be decoded and executed, and the discrete data may be transferred to a continuous data address, or the continuous data may be stored to a plurality of discrete data addresses. As such, a vector computation of the discrete data and vector data restoration after the vector computation may be implemented, which may simplify a processing process, thereby reducing data overheads. In addition, according to the embodiments of the disclosure, when the discrete data is read, by caching a storage address corresponding to a read request, a read request of each piece of data may be merged to read one or more pieces of discrete data, thereby improving reading efficiency of the data.
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公开(公告)号：US11934337B2
公开(公告)日：2024-03-19
申请号：US17419819
申请日：2020-08-31
发明人： Yao Zhang , Shaoli Liu , Dong Han
CPC分类号： G06F13/4282 , G06F13/28 , G06F13/4004 , G06F13/4063
摘要： An electronic device includes a CPU, an acceleration module, and a memory. The acceleration module is communicatively connected with the CPU, and includes chips. The chip according to an embodiment includes a data bus, and a memory, a data receiver, a computing and processing unit, and a data transmitter connected to the data bus. The data receiver receives first data and header information from outside, writes the first data to a corresponding area of the memory through the data bus, and configures a corresponding computing and processing unit and/or data transmitter according to the header information. The computing and processing unit receives first task information, performs an operation processing according to the first task information and a configuration operation on the data transmitter. The data transmitter obtains second task information and second data, and outputs third data to outside based on at least part of the second data.
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3.发明申请公开(公告)号：US20220391665A1
公开(公告)日：2022-12-08
申请号：US17622706
申请日：2020-09-22
发明人： Xiao ZHANG , Yusong ZHOU , Xiaofu MENG
IPC分类号： G06N3/04
摘要： Embodiments of the present disclosure provide a method for splitting a neural network model to be processed by a multi-core processor and related products. When a splittable operator is present in the neural network model, the operator is split, and an optimal splitting combination is selected to obtain an optimal splitting result of an entire neural network model, and then sub-operators corresponding to the optimal splitting result are executed through multiple cores in parallel. Thereby, a purpose of reducing resource consumption of a computer device is achieved.
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公开(公告)号：US20220366006A1
公开(公告)日：2022-11-17
申请号：US17619795
申请日：2020-10-22
发明人： Yao ZHANG , Shaoli LIU
摘要： The present disclosure relates to a computing apparatus, a method and an integrated circuit chip for a vector inner product, where the computing apparatus may be included in a combined processing apparatus. The combined processing apparatus may further include a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage apparatus, where the storage apparatus is respectively connected to the computing apparatus and other processing apparatus, and the storage apparatus is used for storing data of the computing apparatus and other processing apparatus.
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5.发明申请公开(公告)号：US20220350569A1
公开(公告)日：2022-11-03
申请号：US17620547
申请日：2020-10-22
发明人： Yao ZHANG , Shaoli LIU
摘要： The present disclosure relates to a computing apparatus, a method, an integrated circuit chip and an integrated circuit device for performing a neural network operation. The computing apparatus may be included in a combined processing apparatus. The combined processing apparatus may further include a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete calculation operations specified by users. The combined processing apparatus may further include a storage apparatus. The storage apparatus is respectively connected to the computing apparatus and other processing apparatus, and the storage apparatus is used for storing data of the computing apparatus and other processing apparatus. Solutions of the present disclosure may be widely applied to various floating-point data computations.
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公开(公告)号：US20220326947A1
公开(公告)日：2022-10-13
申请号：US17620562
申请日：2020-10-22
发明人： Yao ZHANG , Shaoli LIU
摘要： The present disclosure relates to a converter for data type conversion, a method for data type conversion, an integrated circuit chip, and a calculation apparatus, where the calculation apparatus may be included in a combined processing apparatus, where the combined processing apparatus may further include a general interconnection interface and other processing apparatus. The calculation apparatus interacts with other processing apparatus to jointly complete calculation operations specified by users. The combined processing apparatus may further include a storage apparatus. The storage apparatus is respectively connected to the calculation apparatus and other processing apparatus, and the storage apparatus is used for storing data of the calculation apparatus and other processing apparatus. A solution of the present disclosure may be widely applied to various data type conversion applications.
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公开(公告)号：US20220230069A1
公开(公告)日：2022-07-21
申请号：US17557802
申请日：2022-02-03
发明人： Yufeng GAO , Shibing ZHU
摘要： This disclosure relates to a device, a board card, a method and a readable storage medium for performing sparse training on a neural network model, wherein a processing device of the present disclosure is included in an integrated circuit device, and the integrated circuit device comprises a universal interconnection interface and a computation device. The computation device interacts with the processing device to jointly complete computing operations specified by the user. The integrated circuit device further comprises a storage device, and the storage device is connected to the computation device and the processing device, respectively, for data storage of the computation device and the processing device.
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公开(公告)号：US20210264270A1
公开(公告)日：2021-08-26
申请号：US17254998
申请日：2020-08-20
发明人： Shaoli LIU , Shiyi ZHOU , Xishan ZHANG , Hongbo ZENG
摘要： The present disclosure provides a data processing method, a board card device, a computer equipment, and a storage medium. The board card provided in the present disclosure includes a storage device, an interface apparatus, a control device, and an artificial intelligence chip of a data processing device, where the artificial intelligence chip is connected to the storage device, the control device, and the interface apparatus, respectively. The control device is configured to monitor a state of the artificial intelligence chip. According to the embodiments of the present disclosure, the data to be quantized is quantized according to the corresponding quantization parameter, which may reduce the storage space of data while ensuring the precision, ensure the precision and reliability of the operation result, and improve the operation efficiency.
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公开(公告)号：US12112257B2
公开(公告)日：2024-10-08
申请号：US17137981
申请日：2020-12-30
发明人： Shaoli Liu , Shiyi Zhou , Xishan Zhang , Hongbo Zeng
摘要： The present disclosure provides a data processing method, a data processing device, a computer equipment, and a storage medium. The data processing device includes a board card and the board card provided in the present disclosure includes a storage component, an interface device, a control component, and an artificial intelligence chip of a data processing device. According to the data processing method, the data processing device, the computer equipment, and the storage medium provided in the embodiments of the present disclosure, data to be quantized is quantized according to a corresponding quantization parameter, which may reduce the storage space of data while ensuring the precision, as well as ensure the accuracy and reliability of the operation result and improve the operation efficiency.
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10.发明公开公开(公告)号：US20240289092A1
公开(公告)日：2024-08-29
申请号：US17620583
申请日：2020-10-13
发明人： Yao ZHANG , Shaoli LIU
IPC分类号： G06F7/523
CPC分类号： G06F7/523
摘要： The present disclosure relates to a multiplier, a method, an integrated circuit chip, and a computation apparatus for a floating-point computation. The computation apparatus is included in a combined processing apparatus. The combined processing apparatus further includes a universal interconnection interface and other processing apparatus. The computation apparatus interacts with other processing apparatus to jointly complete computing operations specified by the user. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and other processing apparatus and is used for storing data of the computation apparatus and other processing apparatus. Solutions of the present disclosure is widely used in various floating-point data computations.
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